tag: Mentor

Blog Review: June 27
By Jesse Allen - 27 Jun, 2018 - Comments: 0

Applied Materials' Sundeep Bajikar argues that to realize the full potential of AI, new computing architectures are necessary, otherwise AI will quickly become unaffordable. Synopsys' Iain Singleton considers why it may not always be necessary to start at the reset state during formal verification and how to use abstractions to get a head start on bug hunting. Cadence's Meera Collier look... » read more

Monday At DAC 2018
By Brian Bailey - 26 Jun, 2018 - Comments: 0

DAC #55 started with rumors flying. Will this be the last DAC as we know it? Is there a huge chasm forming between academia and the industry? Will DAC be able to make it in Las Vegas where there is no local interest? Of course, those who have been in the industry know that this kind of speculation happens every few years, and in the 80s, Las Vegas was a very popular location for DAC. There was ... » read more

The Week In Review: Design
By Jesse Allen - 22 Jun, 2018 - Comments: 0

Tools Synopsys revealed a power analysis solution for early SoC design as well as signoff-accurate power and reliability closure. PrimePower has reliability as a major focus, expanding power and reliability signoff and ECO closure capabilities from physical awareness to cell electromigration effects. Supported power types include peak power, average power, clock network power, leakage power, a... » read more

Defining Edge Memory Requirements
By Ann Mutschler - 20 Jun, 2018 - Comments: 0

Defining edge computing memory requirements is a growing problem for chipmakers vying for a piece of this market, because it varies by platform, by application, and even by use case. Edge computing plays a role in artificial intelligence, automotive, IoT, data centers, as well as wearables, and each has significantly different memory requirements. So it's important to have memory requirement... » read more

Blog Review: June 20
By Jesse Allen - 20 Jun, 2018 - Comments: 0

Mentor's Randy Allen digs into OpenACC, a collection of directives and routines to help a compiler uncover and schedule parallelism, plus an examination of the GCC implementation's performance. Cadence's Paul McLellan takes a look at the shifting opinions on FD-SOI vs. finFET as Dan Hutcheson of VLSI Research finds most see the two as complementary technologies in his latest survey. Synop... » read more

IoT Wireless Battles Ahead
By Brian Bailey - 18 Jun, 2018 - Comments: 0

"The good thing about standards is that there are so many to choose from." – Andrew S. Tanebaum The extended version of that quote adds "furthermore, if you do not like any of them, you can just wait for next year's model." That could not be truer when it comes to IoT and wireless connectivity. Every standards group is rushing to create new versions of existing standards that use less p... » read more

CEO Outlook On Chip Industry (Part 3)
By Ed Sperling - 18 Jun, 2018 - Comments: 2

Semiconductor Engineering sat down with Wally Rhines, president and CEO of Mentor, a Siemens Business; Simon Segars, CEO of Arm; Grant Pierce, CEO of Sonics; and Dean Drako, CEO of IC Manage. What follows are excerpts of that conversation. To view part one, click here. Part two is here. L-R: Dean Drako, Grant Pierce, Wally Rhines, Simon Segars. Photo: Paul Cohen/ESD Alliance SE: Securit... » read more

Three Steps To Low Power Coverage Closure
By Awashesh Kumar - 18 Jun, 2018 - Comments: 0

By Awashesh Kumar and Madhur Bhargava Low-power design and verification is becoming more complex. Yet it is critical that all power elements are verified, and it is even more important to verify the complex interactions between these elements at a high abstraction level. However, power-aware coverage closure is difficult to attain and complex by nature. Existing low-power coverage methodo... » read more

The Week In Review: Design
By Jesse Allen - 15 Jun, 2018 - Comments: 0

M&A MIPS has reportedly been acquired again, this time by AI startup Wave Computing. Wave focuses on data center-based neural network training using its parallel dataflow processing architecture. In March, the company signed on to use 64-bit multi-threaded processor cores from MIPS in future projects. Previously, MIPS was owned by Tallwood Venture Capital, which acquired MIPS from Imaginat... » read more

Chip Dis-Integration
By Brian Bailey - 14 Jun, 2018 - Comments: 2

Just because something can be done does not always mean that it should be done. One segment of the semiconductor industry is learning the hard way that continued chip integration has a significant downside. At the same time, another another group has just started to see the benefits of consolidating functionality onto a single substrate. Companies that have been following Moore's Law and hav... » read more

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