tag: Mentor

Blog Review: Oct. 4
By Jesse Allen - 04 Oct, 2017 - Comments: 0

Synopsys' Prishkrit Abrol digs into how USB Type-C Alternate Mode allows MHL, DisplayPort, HDMI, and Thunderbolt over cable. Mentor's Paul Morrison dives into how hardware emulation can help verify the complexities of new storage devices. Cadence's Madhavi Rao listens in as Somshubhro Pal Choudhury of Bharat Innovations describes the IoT stack, hype cycle, and why it's happening now. R... » read more

Prototypes Proliferate
By Brian Bailey - 02 Oct, 2017 - Comments: 0

Hardware prototyping and [getkc id="30" kc_name="emulation"] have been two sides of the same coin ever since the [gettech id="31071" comment="FPGA"] became a commercial success. Early emulators were all built from FPGAs, and most were used in-circuit, much like prototypes are today. More recently, emulation has become a major piece of the [getkc id="10" kc_name="verification"] flow, to the poin... » read more

The Week In Review: Design
By Jesse Allen - 29 Sep, 2017 - Comments: 0

M&A Imagination will sell its MIPS business to Tallwood, a California-based venture capital firm, for $65m in cash. The sale is expected to close in October. The rest of Imagination is slated to be sold to Canyon Bridge for £550 million in cash (~$740 million), a deal dependent on the MIPS sale. The Chinese-backed investment firm has featured recently in the news for its attempted purchas... » read more

Get To Know The Gate-Level Power Aware Simulation
By Progyna Khondkar - 28 Sep, 2017 - Comments: 1

The post-synthesis gate-level netlist (GL-netlist) based PA simulation input requirements are mostly the same as RTL simulation. However, the design under verification here is the GL-netlist from synthesis, so logic gates from standard, MV and Macro cell Liberty libraries are already inserted or instantiated in the design. Hence power aware simulation (PA-SIM) at post-synthesis also requires Li... » read more

System Coverage Undefined
By Brian Bailey - 28 Sep, 2017 - Comments: 1

When is a design ready to be taped out? That has been one of the toughest questions to confront every design team, and it's the one verification engineers lose sleep over. Exhaustive [getkc id="56" kc_name="coverage"] has not been possible since the 1980s. Several metrics and methodologies have been defined to help answer the question and to raise confidence that important aspects of a block... » read more

Verification’s Breaking Points
By Ann Mutschler - 28 Sep, 2017 - Comments: 2

Verification efficiency and speed can vary significantly from one design to the next, and that variability is rising alongside growing design complexity. The result is a new level of unpredictability about how much it will cost to complete the verification process, whether it will meet narrow market windows, and whether quality will be traded off to get a chip out on time in the hopes that it c... » read more

Linux Security Primer: SELinux And SMACK Frameworks
By Mentor, a Siemens Business - 27 Sep, 2017 - Comments: 0

With the increased expansion of the IoT, software developers are called upon to do more to protect their devices from malicious attacks. Building a secure system involves many components and layers of security. This paper offers an introductory review of two popular Linux security frameworks: SELinux and SMACK. Readers will gain an understanding of these two frameworks and when to best implemen... » read more

Plugging Gaps In Advanced Packaging
By Ann Mutschler - 27 Sep, 2017 - Comments: 0

The growing difficulty of cramming more features into an SoC is driving the entire chip industry to consider new packaging options, whether that is a more complex, integrated SoC or some type of advanced packaging that includes multiple chips. Most of the work done in this area so far has been highly customized. But as advanced packaging heads into the mainstream, gaps are beginning to appea... » read more

Blog Review: Sept. 27
By Jesse Allen - 27 Sep, 2017 - Comments: 0

Synopsys' Mukul Dawar highlights the biggest changes coming to the PCIe 4.0 specification, plus a peek at what's new in PCIe 5.0. Cadence's Paul McLellan considers why EDA startups are less common than they used to be. Mentor's David Abercrombie and Alex Pearson discuss new requirements for detecting double patterning errors at advanced nodes. Rambus' Aharon Etengoff reports that secur... » read more

Power Modeling And Analysis
By Brian Bailey - 27 Sep, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss power modeling and analysis with [getperson id="11489" p_name="Drew Wingard"], CTO at [getentity id="22605" e_name="Sonics"]; [getperson id="11763" comment="Tobias Bjerregaard"], CEO at [getentity id="22908" e_name="Teklatech"]; Vic Kulkarni, vice president and chief strategy officer at [getentity id="22021" e_name="Ansys"]; Andy Ladd, CEO of Baum; ... » read more

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