tag: Mentor

Hardware/Software Tipping Point
By Brian Bailey - 08 Jun, 2017 - Comments: 0

It doesn't matter if you believe [getkc id="74" comment="Moore's Law"] has ended or is just slowing down. It is becoming very clear that design in the future will be significant different than it is today. Moore's law allowed the semiconductor industry to reuse design blocks from previous designs, and these were helped along by a new technology node—even if it was a sub-optimal solution. I... » read more

Blog Review: June 7
By Jesse Allen - 07 Jun, 2017 - Comments: 0

Cadence's Paul McLellan listens in on Jeff Bier's Embedded Vision Summit keynote, where he argues the cost and power consumption of vision computing will decrease by about 1000X in the next three years. Synopsys' Sean Safarpour points to three reasons formal has grown in the last ten years to become a standard part of the verification toolbox. Mentor's Matthew Balance checks out the abili... » read more

Security Issues Up With Heterogeneity
By Ann Mutschler - 05 Jun, 2017 - Comments: 0

The race toward heterogeneous designs is raising new security concerns across the semiconductor supply chain. There is more IP to track, more potential for unexpected interactions, and many more ways to steal data or IP. Security is a difficult problem no matter what kind of chip is involved, and it has been getting worse as more devices, machines and systems are connected to the Internet. B... » read more

Implementing High-Density-Advanced Packaging For OSATs And Foundries
By Mentor, a Siemens Business - 05 Jun, 2017 - Comments: 0

HDAP design and verification require cooperation and collaboration between design houses, OSATs, foundries, and EDA vendors. By using common tools that have the integration and functionality needed to operate in both the IC and packaging domains and by developing and deploying process optimized design-kits such as ADK’s and PDKs, OSATs, foundries, and their customers can achieve design, fabri... » read more

Testing IoT Devices
By Jeff Dorsch - 05 Jun, 2017 - Comments: 3

Internet of Things devices present new challenges in testing. Some devices can be tested the same way as standard semiconductors are now tested, but others call for different approaches. Microcontrollers and other chips that go into safety-critical applications — medical devices, military/aerospace systems, and automotive electronics — need their own kind of testing to make sure they wil... » read more

What Happened To Aftermarket Car Audio?
By Ann Mutschler - 01 Jun, 2017 - Comments: 1

With the myriad changes afoot in automotive today, it’s interesting to note that there is significant technology development in the area of audio. Who knew? Considering that we are interacting more with our vehicles today in the form of hands-free technologies, it’s actually not surprising in the least. With all of the features being added to the automobile that add complexity, there is ... » read more

Automotive Features Prominently At DAC 2017
By Andrew Macleod - 01 Jun, 2017 - Comments: 0

Excellent automotive content features prominently at DAC 2017, which starts June 18th in my hometown of Austin. This of course is fitting given that Austin hosted the world’s first truly self-driving car ride just a few months ago. Our mayor, Steve Adler, called Austin the “the Kitty Hawk of driverless cars,” proving he has a future in tech marketing once he’s done with public service. ... » read more

Blog Review: May 31
By Jesse Allen - 31 May, 2017 - Comments: 0

Mentor's Michael White predicts that 10nm will come on the scene in a big way this year with a leap to an estimated 9% foundry market share. At the recent RISC-V Workshop, Cadence's Paul McLellan considers whether fully open-source silicon is really viable. Synopsys' Robert Vamosi investigates the security risks posed by the proliferation of connected aftermarket automotive products and a... » read more

The Week In Review: Design
By Jesse Allen - 26 May, 2017 - Comments: 0

Tools Startup Austemper Design unveiled a functional safety tool suite that includes safety analysis that applies default values from industry standards ISO26262 and/or IEC61508 for Failures-in-Time (FIT) rates, tools to handle safety synthesis and augment design structures, and a parallel fault simulator with hybrid simulation capabilities. SystemVerilog and VHDL parsers from Verific serve ... » read more

Respecting Reset
By Brian Bailey - 25 May, 2017 - Comments: 0

Resets are a necessary part of all synchronous designs because they allow them to be brought into a known state. However, such a simple process can lead to many problems within an [getkc id="81" kc_name="SoC"]. No longer can reset be considered a simple operation when power initially is applied to a circuit. Instead, the design of reset has many implications on cost, area and routability, a... » read more

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