tag: MIPS

Experts At The Table: Multi-Core And Many-Core
By Ed Sperling - 21 Jul, 2011 - Comments: 0

By Ed Sperling Low-Power Engineering sat down with Naveed Sherwani, CEO of Open-Silicon; Amit Rohatgi, principal mobile architect at MIPS; Grant Martin, chief scientist at Tensilica; Bill Neifert, CTO at Carbon Design Systems; and Kevin McDermott, director of market development for ARM’s System Design Division. What follows are excerpts of that conversation. LPE: Computers aren’t gettin... » read more

The Impact Of Triple Play
By Ed Sperling - 12 May, 2011 - Comments: 0

By Ann Steffora Mutschler Not so long ago there were multiple networks that supported different kinds of traffic—a telecommunications network based on high-reliability protocols, the Internet for burst-centric data traffic and video distribution networks. From the consumer standpoint that was highly inefficient. Managing three subscriptions from three service providers was unnecessary, w... » read more

Mobile Applications Drive New Architectures
By Ed Sperling - 28 Apr, 2011 - Comments: 0

By Pallab Chatterjee The push toward mobility in consumer devices is having an impact on the entire component flow. Mobile devices are dominated by two key factors—an overriding power constraint and very high data bandwidth. The power constraints are on the mobile device side and on the cloud-based support server side. The high data bandwidth issues are due to the limited processing powe... » read more

SoC Ecosystems Become More Tightly Integrated
By Ed Sperling - 28 Apr, 2011 - Comments: 0

By Ed Sperling SoC ecosystems are changing. Quality and focus are replacing volumes of names as companies that fund them begin to narrow down which partners add the most value and which markets they need to target. Establishing a ring of allies is nothing new, of course. IBM had its circle of most trusted software partners back in the 1970s when mainframes were the dominant computing platfo... » read more

The Quest For A Better IP Integration Methodology
By Ed Sperling - 31 Mar, 2011 - Comments: 0

By Ed Sperling With the amount of IP in SoC designs now hitting an estimated 70% to 90%, companies are scrambling to figure out a way to more consistently integrate that IP and to test that it will work as expected. This is easier said than done, however, for a number of reasons: There are numerous types of IP, ranging from I/O to logic and memory. Not all IP is of equal quality. ... » read more

Experts At The Table: Billion-Gate Design Challenges
By Ed Sperling - 25 Mar, 2011 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to discuss billion-gate design challenges with Charles Janac, CEO of Arteris; Jack Browne, senior vice president of sales and marketing at Sonics; Kalar Rajendiran, senior director of marketing at eSilicon; Mark Throndson, director of product marketing at MIPS; and Mark Baker, senior director of business development at Magma. What follows are excer... » read more

Power Panel: IP And Other Key Issues For Future Development
By Ed Sperling - 17 Mar, 2011 - Comments: 0

By Ed Sperling Low-Power Engineering chaired a DesignCon panel of low-power experts with Bhanu Kapoor, president of Mimasic; Kesava Talupuru, DV engineer at MIPS; Prapanna Tiwari, CAE manager at Synopsys, and Rob Aitken, an ARM Fellow. What follows are excerpts of their presentations and the panel discussion that followed. Prapanna Tiwari: UPF and CPF are text files that capture the power i... » read more

The True Test Of IP Reuse
By Ed Sperling - 17 Mar, 2011 - Comments: 0

By Ann Steffora Mutschler Fewer and fewer systems and semiconductor companies are designing brand new processors from scratch. Instead, they leverage as much IP as possible in their designs, investing selectivity in areas where they can add significant value. The challenges are varied from low-power issues to process technology migrations. Generally, IP consumers are doing two levels of IP-... » read more

Experts At The Table: Billion-Gate Design Challenges
By Ed Sperling - 17 Mar, 2011 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to discuss billion-gate design challenges with Charles Janac, CEO of Arteris; Jack Browne, senior vice president of sales and marketing at Sonics; Kalar Rajendiran, senior director of marketing at eSilicon; Mark Throndson, director of product marketing at MIPS; and Mark Baker, senior director of business development at Magma. What follows are excer... » read more

Billion-Gate Chips
By Ed Sperling - 16 Mar, 2011 - Comments: 0

Low-Power Engineering examines hurdles ranging from power to cost in billion-gate IC designs with Arteris; Jack Browne, senior vice president of sales and marketing at Sonics; Kalar Rajendiran, senior director of marketing at eSilicon; Mark Throndson, director of product marketing at MIPS; and Mark Baker, senior director of business development at Magma. [youtube vid=0jum2ThIVzg] » read more

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