tag: models

Cars, Security, And HW-SW Co-Design
By Jeff Dorsch - 31 Aug, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss parallel hardware/software design with Johannes Stahl, director of product marketing, prototyping and FPGA, [getentity id="22035" e_name="Synopsys"]; [getperson id="11411" comment="Bill Neifert"], director of models technology, [getentity id="22186" comment="ARM"]; Hemant Kumar, director of ASIC design, Nvidia; and Scott Constable, senior member of ... » read more

Does Power Analysis Need To Be Accurate?
By Ann Mutschler - 11 Aug, 2016 - Comments: 1

The mere mention of accuracy in power analysis and optimization today can trigger a contentious discussion, even among typically reserved engineers. What is needed and where? Which tools are truly as accurate as claimed? And how much accuracy is actually needed for power analysis, [getkc id="112" kc_name="estimation"], and optimization? First of all, the accuracy required really depends o... » read more

Models Are Dead? Long Live Models
By Frank Schirrmeister - 28 Jul, 2016 - Comments: 0

During the first half of this year I had more discussions with customers on models again. Are models back? For what purpose? In short, it looks like models are well adopted and in use for software development. For performance and architecture analysis, however, as a recent presentation from Renesas at CDNLive Japan shows, users just use RTL as that accuracy is required. In combination with emul... » read more

Hardware Models For Software
By Brian Bailey - 24 Nov, 2015 - Comments: 1

Shift left, while a relatively new term, has become important in all parts of the SoC design flow, but its impacts are wide ranging and many still ill defined. It basically means that tasks have to be started earlier than in the past because more accuracy is required from tasks that are further down in the flow in order to make better predictions. It also implies that more steps are performed c... » read more

Abstraction: Necessary But Evil
By Brian Bailey - 14 Oct, 2015 - Comments: 1

Abstraction allows aspects of a design to be described in an executable form much earlier in the flow. But some abstractions are breaking down, and an increasing amount of lower-level information has to be brought upstream in order to provide estimates that are close enough to reality so informed decisions can be made. The value of abstractions in design cannot be overstated. High levels of ... » read more

Virtual Prototyping Takes Off
By Ed Sperling - 06 Nov, 2014 - Comments: 0

Semiconductor Engineering sat down with Barry Spotts, senior core competency FAE for fabric and tools at [getentity id="22186" comment="ARM"]; Vasan Karighattam, senior director of architecture for SoC and SSW engineering at [getentity id="22664" e_name="Open-Silicon"]; Tom De Schutter, senior product marketing manager for Virtualizer Solutions at [getentity id="22035" e_name="Synopsys"]; Larry... » read more

Are Models Holding Back New Methodologies?
By Brian Bailey - 30 Oct, 2014 - Comments: 1

Semiconductor Engineering sat down to discuss the state of the industry for [getkc id="101" kc_name="modeling"] at abstractions above [getkc id="49" kc_name="RTL"], a factor which has delayed adoption of [getkc id="104" kn_name="virtual prototypes"] and the proliferation of system-level design and hardware/software codesign. Taking part in the discussion were Frank Schirrmeister, group director... » read more

Raising The IP Abstraction Level
By Ed Sperling - 25 Jul, 2013 - Comments: 0

By Ed Sperling An increasing reliance on commercial and re-used IP and more emphasis placed on software development is adding even more pressure onto semiconductor design teams to figure out the benefits and limitations of myriad possible choices earlier in the design process. Design teams already are under pressure to meet increasingly tighter market deadlines, and it is stressing every pa... » read more

The Best Abstraction
By Jon McDonald - 28 Mar, 2013 - Comments: 0

By Jon McDonald The other day I was asked what would be the best level of abstraction to model at for system-level design. This is a question I get, in one form or another, far too often. It reminds me of an old quote attributed to Lincoln, slightly updated and applied to this subject: “One model can answer some of the questions all of the time, and all of the questions some of the time, but... » read more

Interface Additions To The e Language For Effective Communication With SystemC TLM 2.0 Models
By Various Writers - 23 Aug, 2012 - Comments: 0

The last several years have seen strong adoption of transaction-level models using SystemC TLM 2.0. Those models are used for software validation and virtual prototyping. For functional verification, TLMs have a number of advantages—they are available earlier, they allow usersto divide their focus on verifying functionality and protocol/timing details, they enable higher level reuse, and they... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy