Auto Security Accelerates With Standardization And Certified Silicon


Key Takeaways The automotive sector is actively developing and delivering secure parts and features ranging from secure boot to encrypted data and in-network protections. The cost of a breach can involve everything from ransomware to liability and/or damage to a brand. New standards are being introduced to ensure security, and technology developers are integrating cybersecurity requi... » read more

Limiting AI/ML Tools To Ensure Physical AI Safety, Security


Key Takeaways: AI-based tools can help monitor physical AI systems and LLMs, but human oversight is still needed to avoid false positives, bias, and other anomalies. For autonomous vehicles and robots, edge case scenarios and understanding human values are weak points, especially as moral and social values change over time. AI tools are growing and becoming increasingly helpful for c... » read more

New Automotive Architectures Are Shaking Up Processor And Memory Choices


Key Takeaways Assisted and autonomous driving require more data from more sensors, and much faster processing of some of that data. The shift to software-defined vehicles and centralized intelligence makes it easier to identify where the most advanced processors and memories are required, and where older and less expensive technologies can be deployed. Technologies that were largely ... » read more

Multi-Channel Ultra Ethernet TSS Complete Layer


In the data center environment, the servers, storage and AI/HPC clusters need to move confidential data quickly and securely. Traditionally, RDMA is used as a transport protocol along with the network security based on MACsec and IPsec ESP protocols. To improve efficiency of using Ethernet in AI/HPC systems, the Ultra Ethernet Consortium introduced the new, IP-based transport protocol (UET), al... » read more

Chip Industry Week in Review


The IEEE ISSCC conference was held this week in San Francisco. Among the highlights: IBM detailed an AI accelerator based on its new inferencing dataflow architecture. CEA-Leti presented a chip-scale, ultra-fast, battery-operated EPR spectrometer. QuTech introduced a cryo-CMOS SoC with NV centers in diamond. UTokyo showed its low-jitter PLL architecture for beyond 5G/6G. Imec d... » read more

AI Inference Needs A Mix-And-Match Memory Strategy


AI inference is no longer a single workload that can be served efficiently by a single type of accelerator or memory. From fast chat replies to 10M token codebases, inference spans wildly diverse workloads with very different limits on latency, bandwidth, capacity, and compute, as the figure below demonstrates.1 Source: Meta1 The AI inference spectrum of workloads includes: Inter... » read more

Minimum Energy Per Query


Key Takeaways Extracting heat from a chip faster is a short-term fix to a bigger problem. The longer-term challenge is how to reduce the amount of energy used per query. Data movement, guardbanding, and software inefficiency are key targets for the future. Heat is a serious problem within AI chips, and it is limiting how much processing can be done. The solution is either to... » read more

Chip Industry Week in Review


Intel hired ex-Qualcomm GPU guru Eric Demers for the company's high-performance GPU push, setting the stage for a three-way battle with Nvidia and AMD. The key targets for Intel and AMD will be better power efficiency and a programming model that rivals CUDA, but don't expect Nvidia to stand still. Acquisitions Texas Instruments plans to acquire Silicon Labs for ~$7.5B cash to enhance i... » read more

Securing Hardware For The Quantum Era


Key Takeaways: Quantum threats to security are already real. Adversaries are already harvesting data that will be decrypted later by quantum computers. Quantum computers capable of breaking RSA and ECC may arrive as early as next year. Asymmetric encryption algorithms like RSA and ECC will become inadequate against quantum threats, while symmetric encryption (such as AES) is less vul... » read more

From Monolithic SoCs To Chiplets: A New Hardware Security Paradigm


Chiplet architectures are quickly becoming the dominant approach for building scalable, heterogeneous SoCs. By disaggregating a monolithic die into multiple interoperable chiplets, silicon designers gain flexibility in process node choices, reuse of proven functions, and faster time-to-market. At the same time, disaggregation breaks one of the most fundamental assumptions in traditional SoC sec... » read more

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