As Chiplets Go Mainstream, Chip Industry Players Collaborate to Overcome New Development Challenges


The semiconductor industry is building a comprehensive chiplet ecosystem to seize on the advantages of the devices over traditional monolithic system-on-chips (SoCs) such as improved performance, lower power consumption, and greater design flexibility. With heterogeneous integration (HI) presenting significant challenges, collaboration to fulfill the potential of chiplets has become even more i... » read more

Blog Review: Feb. 15


Siemens EDA's Harry Foster examines the relationship between verification maturity and non-trivial bug escapes into production, as well as whether safety critical development processes yield higher quality in terms of preventing bugs and achieving silicon success. Synopsys' Shankar Krishnamoorthy finds that the rapid progress of machine learning models is driving demand for more domain-speci... » read more

Week In Review: Semiconductor Manufacturing, Test


Chips for consumer devices are down, but the overall chip industry is actively preparing for the next phase of growth. Worldwide silicon wafer shipments, which are an aggregate view of all the various semiconductor segments, hit an all-time high in 2022, increasing 4% to 14,713 million square inches (MSI). Wafer revenue, meanwhile, rose 9.5% to $13.8 billion over the same period, SEMI reported ... » read more

Week In Review: Design, Low Power


Arm is heading for an IPO this year, with plans "fairly well developed and underway now," CEO Rene Haas told Reuters. Arm reported fiscal Q3 revenue of $746 million, up 28% compared with the same period in 2021, setting the stage for a public offering. The company noted it had double- or triple-revenue increases in automotive, consumer, infrastructure, and IoT. The Si2 Compact Model Coalit... » read more

Blog Review: Feb. 8


Cadence's Sanjeet Kumar points to key changes and optimizations that are done for USB3 Gen T compared to USB3 Gen X tunneling in order to minimize tunnel overhead and maximize USB3 throughput. Siemens EDA's Harry Foster considers the effectiveness of IC and ASIC verification by looking at schedule overruns, number of required spins, and classification of functional bugs. Synopsys' Chris C... » read more

Big Changes Ahead For Chip Technology And Industry Dynamics


Semiconductor Engineering sat down to discuss the impact of customization and advanced packaging, and concerns about reliability and geopolitical rivalries with Martin van den Brink, president and CTO of ASML; Luc Van den Hove, CEO of imec; David Fried, vice president of computational products at Lam Research; and Ankur Gupta, vice president and general manager of the test group and lifecycle s... » read more

Startup Funding: January 2023


Quantum computing had a good month in January, collectively raising over $240 million. A significant chunk of that went to a full-stack quantum company whose processers use neutral atoms manipulated by optical tweezers. Other companies funded this month are developing trapped ion processors, photonics-based processors, and quantum memories, which will be essential for quantum networking. Two co... » read more

Blog Review: Feb. 1


Siemens EDA's Harry Foster explores trends in low power design techniques for ICs and ASICs, with 72% of design projects reported actively managing power. Synopsys' Charlie Matar, Rita Horner, and Pawini Mahajan look at the concept of reliability, availability, and serviceability (RAS) in the context of high-performance computing SoC designs and how it can be supported with silicon lifecycle... » read more

Week In Review: Design, Low Power


Electronic system design (ESD) industry revenue is up 8.9% from $3,458.2 million in Q3 2021 to $3,767.4 million in Q3 2022 according to a report from SEMI’s ESD Alliance. Read our in-depth take on what this means. In an attempt to make a viable reusable DNA biosensor probe, NIST researchers used an extremely low-power FETdeveloped at CEA-LETI to remove noise in their DNA biosensor circuitr... » read more

Blog Review: Jan. 25


Cadence's Shyam Sharma shares some important design and verification considerations when working with DDR5 SDRAM and DDR5 DIMM-based memory subsystems, including reset and power on initialization, speed bin compliance, and refresh, RFM, and temperature requirements. Siemens EDA's Harry Foster examines trends in adoption of languages and libraries for IC and ASIC design, testbench creation, a... » read more

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