New Rules Put The Squeeze On Semiconductor Gray Market


The shift toward chiplets and multi-die assemblies is forcing big changes in the global supply chain, including much tighter cooperation between companies and governments to ensure the authenticity and quality of semiconductor parts. The chip industry has been looking to digital certificates as the best means of reducing counterfeiting and ensuring consistent quality for some time. The probl... » read more

Chip Industry Week in Review


SK hynix is ramping HBM manufacturing capacity to meet explosive demand for AI data centers. The company will launch 16-stack HBM4 next year, and up to 12-stack HBM4E. HBM5 and HBM5E will be introduced between 2029 and 2031, reports Business Korea. China will not have access to NVIDIA’s most advanced chips, President Trump told 60 Minutes. The Dutch economy minister said Nexperia's chip... » read more

Blog Review: Nov. 5


Synopsys' Igor Markov points out how numerical simulation tools advance quantum computing R&D by capturing both quantum-mechanical behavior and classical electromagnetic effects so researchers can evaluate design alternatives before fabrication and gain insight into how devices operate under realistic conditions. Siemens' Stephen V. Chavez finds that impedance modeling and control are mi... » read more

Chip Industry Week in Review


San Francisco-based Substrate raised more than $100 million to build a vertically integrated foundry that uses particle accelerators to produce "the world's brightest beams, enabling a new method of advanced X-ray lithography." The company claims its technology is comparable to ASML's high NA EUV, and notes it can extend well beyond 2nm. ASML has not publicly commented. The Nexperia chip sho... » read more

Blog Review: Oct. 29


Siemens' Ujjwal Negi and Prashant Dixit warn that while UCIe 3.0 improves performance and efficiency through higher data rates, runtime recalibration, priority sideband messaging, low-power sideband operation, and circular buffer transport, those enhancements also increase verification complexity. Cadence's Anika Sunda suggests that a unified digital thread that connects verification environ... » read more

New Standardized Semiconductor Cybersecurity Assessment (SSCA) Strengthens Security And Collaboration Across Global Supply Chain


The SEMI Semiconductor Manufacturing Cybersecurity Consortium (SMCC) Work Group 3 (Supply Chain Cybersecurity) just released a major work product that will have a significant and lasting positive impact on the industry: the “Standardized Semiconductor Cyber Assessment (SSCA)” questionnaire. Creating a common security assessment process for device makers, equipment suppliers, software s... » read more

Blog Review: Oct. 22


Cadence's Sandip Sadadiya shows what's new in the AMBA AXI Issue L protocol update, which introduces a new credit-based transport mechanism that replaces the traditional VALID/READY handshake, along with improved flow control mechanisms. Siemens' Farhad Ahmed highlights the growing need to do clock domain crossing (CDC) and reset domain crossing (RDC) analysis in a hierarchical way and intro... » read more

Chip Industry Week in Review


The Open Compute Project (OCP) Summit kicked off this week in San Jose, dominated by open standards, massive scaling of AI infrastructure, chiplet architectures, and energy-efficiency. Among the highlights: An initiative to standardize data center infrastructure and advance Ethernet for AI. New contributions to OCP's Open Chiplet Economy ecosystem, including Arm's new Foundation Chiplet... » read more

Chip Industry Week in Review


SEMICON West was held in Phoenix this week, with presentations covering heterogeneous integration, AI, quantum, supply chain resilience, and more. Amid the buzz of the conference, some key manufacturing and test announcements were made this week: The strategic importance of the Phoenix area hub was highlighted. Amkor Technology broke ground this week on its advanced packaging and test camp... » read more

Blog Review: Oct. 8


Siemens' Azat Latypov presents a stochastic-aware optical proximity correction strategy that demonstrated an order-of-magnitude reduction in the probability of stochastic defects for both SRAM and logic designs, sacrificing minor edge placement error in return for much lower failure rates. Cadence's Dimitry Pavlovsky introduces the AMBA CHI Chip-to-Chip (C2C) protocol, which extends the CHI ... » read more

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