Chip Industry Week in Review


Government funding/defunding NIST is terminating funding for the SMART USA Institute, a CHIPS Act research center focused on digital twins, prompting congressional concern that the decision disrupts active awards and weakens U.S. semiconductor R&D commitments. Korea Zinc was awarded $210M in CHIPS Act funding towards a new $6.6B Tennessee advanced smelter and minerals processing facility,... » read more

Advanced Packaging: Driving Innovation, Performance, And New System Capabilities


Advanced packaging is no longer operating behind the scenes. The technology of advanced packaging is helping to sustain the speed of the semiconductor industry’s improvement in power and performance, even as the Moore’s Law roadmap for wafer-level scaling comes under strain. At the Advanced Packaging Conference during SEMICON Europa 2025 in Munich, global experts examined the growth tr... » read more

Blog Review: Dec. 17


Cadence's Shyam Sharma checks out what's new in the latest Open NAND Flash Interface 5.2 standard, including a Separate Command Address protocol that allows Hosts to optimize the command and data scheduling to increase overall available bandwidth. Siemens' Kyle Fraunfelter and Melville Bryant contend that improving semiconductor manufacturing and fab sustainability starts with a digital twin... » read more

Zero-Trust Data Sharing Architectures Redefining Chip Manufacturing


Real-time security clearances are becoming increasingly common in the manufacturing of advanced-node semiconductors, where data sharing is both essential and a potential security threat. Data security is a well-known issue in semiconductor manufacturing, but much of it is based on an outdated approach. In its place, zero-trust architectures [1] are now a requirement for new equipment and ins... » read more

Blog Review: Dec. 3


Cadence's Reela Samuel notes that as multi-die integration becomes the new engine of semiconductor performance, the decision between 2.5D and 3D-IC architectures shapes a design's achievable bandwidth, energy efficiency, thermal limits, system size, and even program schedules. Synopsys' Thomas Andersen suggests that the deployment of physical AI will require the fusion of advanced electronic... » read more

Blog Review: Nov. 26


Cadence's Rajneesh Chauhan explains CXL's low power state, L0p, which maintains partial lane activity for efficient power management without compromising performance, and how comprehensive verification can help ensure reliable implementation. Siemens' John Ferguson provides a brief history of design rule checking, major advancements over the years, and why introducing it in earlier design st... » read more

New Panel Production Efforts Target Interposer Costs


The rising cost of increasingly large interposers is spurring renewed interest in panel-level manufacturing, which for years has hobbled along due to the massive and collective effort required by the chip industry to change formats. Several companies are developing their own processes, although there is currently no commercial production. And a new consortium called Joint3, spearheaded by Ja... » read more

Navigating Geopolitical Shifts And AI-Driven Growth: Insights From The SEMICON West 2025 Market Symposium


By Clark Tseng and Nishita Rao The 2025 SEMICON West Market Symposium brought together leading analysts and strategists to decode the powerful forces shaping the global semiconductor market. Building on last year’s focus on fabless growth and workforce initiatives, this year’s sessions centered on the rising influence of geopolitics, trade policy, and AI-driven investment. Experts from... » read more

Blog Review: Nov. 19


Cadence's Mamta Rana explores how Forward Error Correction in PCIe 6.0 is key to its 64.0 GT/s per lane bandwidth by enabling the receiver to detect and correct errors without retransmissions or protocol-level recovery by adding redundant information to transmitted data. Siemens' Dave Rich shares a paper from DVCon 1992 that introduced a new RTL modeling construct to Verilog, eventually know... » read more

Chip Industry Week in Review


Samsung reportedly is hiking memory chip prices by 30% to 60% due to high demand from AI data centers and constrained supplies. Those shortages are causing ripples elsewhere. SMIC, China's largest foundry, said its customers are holding back orders for other types of semiconductor due to concerns about memory supplies. Meanwhile, interest in photonics and power semiconductors is picking up, ... » read more

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