tag: Siemens EDA

Grappling With Auto Security
By Ann Mutschler - 07 Jul, 2016 - Comments: 1

It’s a changed world under the hood of automobiles today, as vehicles become increasingly connected to infrastructure and each other. But that connectedness also is creating new security risks. Growing complexity is one piece of the problem. There are upwards of 80 electronic control units (ECUs) and more than 100 million lines of code in an average vehicle. On top of that, there are m... » read more

Systems Engineering Approach To Electrical Wire Interconnection System (EWIS) Development
By Mentor, a Siemens Business - 07 Jul, 2016 - Comments: 0

The development of the Electrical Wire Interconnection System, or EWIS, for today’s advanced aircraft is one of the most complicated engineering activities around. In addition to having to respond to very high rates of change during development, the aircraft are continually evolving in electronic and electrical content through their entire lifecycle. Relatively new mandates, such as the CFR P... » read more

Verification Engine Disconnects
By Ed Sperling - 06 Jul, 2016 - Comments: 0

Moving verification data seamlessly between emulation, simulation, FPGA prototyping and formal verification engines may be possible on paper, but it is proving more difficult to implement in the real world. [getkc id="10" kc_name="Verification"] still consumes the most time and money in the design process. And while the amount of time spent on verification in complex designs has held relativ... » read more

Blog Review: July 6
By Jesse Allen - 06 Jul, 2016 - Comments: 0

Cadence's Chris Rowen discusses optimizing neural networks for low-energy and high-throughput applications in his latest video. What should you include in an IoT chip? Synopsys' Eric Huang presents the case for building in USB. Mentor's Matthew Hogan takes a look at what's needed for speedy interconnect robustness verification. Rambus' Aharon Etengoff digs into a potential new enterpri... » read more

GPUs Power Ahead
By Ann Mutschler - 05 Jul, 2016 - Comments: 0

GPUs, long a sideshow for CPUs, are suddenly the rising stars of the processor world. They are a first choice in everything from artificial intelligence systems to automotive ADAS applications and deep learning systems powered by [getkc id="261" kc_name="convolutional neural network"]. And they are still the mainstays of high-performance computing, gaming and scientific computation, to name ... » read more

EDA, IP Sales Up
By Ed Sperling - 30 Jun, 2016 - Comments: 0

EDA and IP revenue increased 4.5% in Q1, a significant increase given the semiconductor industry was flat last year and that EDA sales dropped 1.9% in Q4 of 2015. Total sales were $1.962 billion, up from $1.877 in Q1 of 2015. The big surprise, though, was Japan, which grew 12%. Japan's semiconductor business has been in a deep slump for several years. "It's been a long time since we've se... » read more

Uncertainty Rocks Chip Market
By Ed Sperling - 30 Jun, 2016 - Comments: 1

The semiconductor industry is undergoing sweeping changes in every direction, making it far more difficult to figure out which path to take next, when to take it, and how to get there. The next few years will redefine which semiconductor companies emerge as leaders, which ones get pushed down or out or absorbed into other companies, and which markets will be the most lucrative. And that coul... » read more

Electrical-Mechanical Tool Flow Revisited
By Ann Mutschler - 30 Jun, 2016 - Comments: 0

For many years, the design tool industry has entertained the idea of combining both electrical and mechanical design into a single user experience, with a single database as a foundation. Major tool vendors, at least on the electrical side, have taken the matter seriously and confirm that activities towards a single flow have been considered, particularly as the [getkc id="7" kc_name="EDA"] ... » read more

Improve DFT Verification And Meet Time-To-Market Goals With Emulation
By Steve Dondershine - 30 Jun, 2016 - Comments: 0

What if all the DFT verification on your next big chip could be completed before tape-out? This “shift-left” of DFT verification would eliminate the need for shortcuts in verification and allow for more types of verification. The benefits of faster and earlier DFT verification include higher confidence in the “golden” RTL, eliminating DFT from the critical path of tape-out, and more pre... » read more

Can Verification Meet In The Middle?
By Brian Bailey - 30 Jun, 2016 - Comments: 0

Since the dawn of time for the EDA industry, the classic V diagram has defined the primary design flow. On the left hand side of the V, the design is progressively refined and partitioned into smaller pieces. At the bottom of the V, verification takes over and as you travel up the right-hand side of the V, verification and integration happens until the entire design has been assembled and valid... » read more

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