tag: Siemens EDA

Blog Review: March 30
By Jesse Allen - 30 Mar, 2016 - Comments: 0

Are we in a new wave of formal? Mentor's Joe Hupcey III highlights several things from DVCon that indicate formal is becoming a cornerstone of mainstream verification flows. Synopsys' Graham Etchells continues his search for more ways to bring greater efficiency to the FinFET layout process, and the downsides to custom routing solutions. Cadence's Paul McLellan takes a look at TSMC's rapi... » read more

Manufacturing Bits: March 29
By Mark LaPedus - 29 Mar, 2016 - Comments: 0

Brain-inspired computing Lawrence Livermore National Laboratory (LLNL) has purchased a brain-inspired supercomputing platform for deep learning developed by IBM Research. Based on a neurosynaptic computer chip called IBM TrueNorth, the scalable platform will process the equivalent of 16 million neurons and 4 billion synapses. It will consume the energy equivalent of a tablet computer. ... » read more

Planes, Cars, And Lagging Standards
By Ed Sperling - 28 Mar, 2016 - Comments: 0

Automotive and aerospace standards are struggling to adapt to pervasive connectivity, increased functionality, and new packaging approaches and architectures, leaving chipmakers and systems vendors unsure about what needs to be included in future designs. Each of these markets has a reputation for being lumbering and unresponsive, in part because they deal with safety-critical issues and i... » read more

The Week In Review: Design/IoT
By Jesse Allen - 25 Mar, 2016 - Comments: 0

Numbers EDA sales dropped 1.9% in Q4 of 2015, following a spectacular run of 23 consecutive quarters of solid growth, according to EDAC. For the year, the EDA and IP industry posted 5% growth. At the same time, IP revenue grew 9.2% to $702.2 million, making it the first time ever that IP surpassed CAE revenue. Services revenue also grew 5.4% year over year to 107.1 million. A new report f... » read more

An Unsustainable Divide
By Brian Bailey - 24 Mar, 2016 - Comments: 0

One of the great things about attending DVCon, or any other conference for that matter, is the networking. You get to see so many people who are eager to learn, to talk and to share ideas. When this happens, you tend to hear a lot of statements that have to rattle around in your mind for a while before you can start to make sense of them and see if any coherent themes emerge. By themes, I am... » read more

Enhanced Electro-Mechanical Collaboration
By Alex Grange - 24 Mar, 2016 - Comments: 0

By Alex Grange and Linda Mazzitelli Integrating electronics into its mechanical environment comes with a number of challenges that boil down to Collision and Connectivity (does the cabinet bang against that capacitor?) and Synchronization (is mechanical designing to the latest PCB design and vice versa?). The culprit to problems that arise usually is the result of poor communications. Mod... » read more

Accelerating Design-For-Test Pattern Simulation
By Mentor, a Siemens Business - 23 Mar, 2016 - Comments: 0

The Veloce DFT App presents a true “left shift” improvement for a traditional chip design schedule that requires comprehensive gate-level simulations to develop ATPG, BIST, or functional patterns. It enables running complete patterns for DFT verification in a reasonable time to shorten the pattern development cycle. The Veloce DFT App fits seamlessly into the Veloce ecosystem, enabling a ho... » read more

Blog Review: March 23
By Jesse Allen - 23 Mar, 2016 - Comments: 0

How exactly does a giant fire behave in space? NASA plans to find out, in the latest top five tech picks from Ansys' Justin Nescott. Plus, never scrape ice off your car again and a pangolin-inspired motorcycle helmet. Cadence's Paul McLellan investigates the growing impact of dark silicon as Dennard scaling breaks down and the number of cores in a chip grows. Mentor's Harry Foster present... » read more

The Week In Review: Design/IoT
By Jesse Allen - 18 Mar, 2016 - Comments: 0

Tools Aldec updated its emulation and simulation acceleration software package for high speed prototyping boards, adding a SCE-MI Pipes-based flow for streaming large amounts of data, and a 30% speed increase for all emulation modes. Plus, Aldec's mixed-language FPGA design and simulation platform now includes a complete coverage analysis package for FPGA and ASIC designers with the addition... » read more

Multi-Beam Market Heats Up
By Mark LaPedus - 17 Mar, 2016 - Comments: 3

The multi-beam e-beam mask writer business is heating up, as Intel and NuFlare have separately entered the emerging market. In one surprising move, [getentity id="22846" e_name="Intel"] is in the process of acquiring IMS Nanofabrication, a [gettech id="31058" t_name="multi-beam e-beam"] equipment vendor. And separately, e-beam giant NuFlare recently disclosed its new multi-beam mask writer t... » read more

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