tag: Siemens EDA

Reducing Post-Placement Leakage With Stress-Enhanced Fill Cells
By Valeriy Sukharev - 17 Mar, 2016 - Comments: 0

By Valeriy Sukharev, Jun-Ho Choy, Armen Kteyan and Henrik Hovsepyan As downward scaling of transistors continues, optimizing power consumption for mobile devices is a major concern. Power consumption consists of two components: dynamic and static. Dynamic (active) power is used while the chip is performing various functions, while static (leakage) power is consumed by leakage current (Figure... » read more

Running Out Of Energy?
By Ann Mutschler - 16 Mar, 2016 - Comments: 1

The anticipated and growing energy requirements for future computing needs will hit a wall in the next 24 years if the current trajectory is correct. At that point, the world will not produce enough energy for all of the devices that are expected to be drawing power. A report issued by the Semiconductor Industry Association and Semiconductor Research Corp., bases its conclusions on system-le... » read more

Automotive Semiconductor Test
By Mentor, a Siemens Business - 16 Mar, 2016 - Comments: 0

We are witnessing the gradual transition of the automobile from a simple means of transportation to a mobile electronic hub. The amount of electronic content in passenger cars continues to grow rapidly. Recent reports indicate that electronics now contribute about 40% of the total costs of a traditional, internal combustion engine car, and this jumps as high as 75% for the growing number of ele... » read more

Blog Review: March 16
By Jesse Allen - 16 Mar, 2016 - Comments: 0

A bacterium that chows down on plastic could be a boon to reducing our huge piles of plastic waste, in this week's top five tech picks from Ansys' Bill Vandermark. Plus, silicon photonics got one step closer, keeping an eye on new neurons, and getting around with magnets. Can semiconductors be open sourced? Rambus' Aharon Etengoff considers what that would take, the potential impact on the I... » read more

The Week In Review: Design/IoT
By Jesse Allen - 11 Mar, 2016 - Comments: 0

Legal A federal court jury favored Synopsys in a 2013 lawsuit alleging that ATopTech violated copyright by copying elements of the command set for Synopsys' PrimeTime static timing analysis product. Synopsys was awarded $30.4 million in damages. ATopTech plans to contest the verdict, stating that other issues in the case remain to be decided. Tools Aldec unveiled the latest version of ... » read more

IP Risk Sharing
By Brian Bailey - 10 Mar, 2016 - Comments: 0

For most people within the semiconductor industry, managing risk involves making the right product decisions that will enable a company to be profitable, and ensuring the product is successfully produced within the necessary time window. In contrast, for products within high-risk areas such as medical and mil/aero, design often proceeds at a slower pace, using proven technologies and adopting l... » read more

Mixed-Signal Design Powers Ahead
By Ann Mutschler - 10 Mar, 2016 - Comments: 1

Mixed-signal devices are at the heart of many advanced systems today because of the need to interact with the outside world, but designing and verifying these systems is getting harder. There are several reasons for this. First, almost all of these devices now have to be lower power than in the past, and in the analog space it's not as simple as just dialing down part of a block. Second, it ... » read more

Power Analysis Plus Power Management
By Ellie Burns - 10 Mar, 2016 - Comments: 0

In my earlier blogs we've heard from some of the experts on using UPF in the successive refinement flow. We’ve talked about controlling leakage power, bringing power down, and validating power management behavior using coverage and simulation, including debug and clock domain crossing verification. In order to do the last step in the successive refinement flow, you need to use emulation be... » read more

Verification Facing Unique Inflection Point
By Brian Bailey - 10 Mar, 2016 - Comments: 0

The Design and Verification Conference and Exhibition (DVCon) attracted more than 1,100 people to San Jose last week, just slightly less than last year. While a lot of focus, and most of the glory, goes to design within semiconductor companies, it is verification where most of the advancements are happening and thus the bigger focus for DVCon. The rate of change in verification and the producti... » read more

How Many Cores? (Part 1)
By Ed Sperling - 10 Mar, 2016 - Comments: 2

The optimal number of processor cores in chip designs is becoming less obvious, in part due to new design and architectural options that make it harder to draw clear comparisons, and in part because just throwing more cores at a problem does not guarantee better performance. This is hardly a new problem, but it does have a sizable list of new permutations and variables—right-sized heteroge... » read more

← Older posts Newer posts →

  • Sponsors

  • Standards/Organizations

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy