tag: Siemens

Tuesday At DAC
By Brian Bailey - 21 Jun, 2017 - Comments: 0

Accellera got everyone out of bed early this morning to talk about the just announced early access release of Portable Stimulus. The panel was made up with people from user companies. Semiconductor Engineering will be providing full coverage of this event, but perhaps the important message is that the panelists were eager to get adoption within their companies but knew that there would be chall... » read more

Blog Review: June 21
By Jesse Allen - 21 Jun, 2017 - Comments: 0

Mentor's John McMillan looks into the unique form-factors and components influencing IoT PCB designs. Cadence's Paul McLellan notes some big topics at the Samsung Foundry Forum: FD-SOI, embedded MRAM, and which gate-all-around FET architecture may be the winner. Synopsys' Eric Huang has a lighthearted look at why to buy IP versus building it. Rambus' Aharon Etengoff points to another U... » read more

Monday At DAC
By Brian Bailey - 20 Jun, 2017 - Comments: 1

The 54th DAC got started today in a very steamy Austin. While we may be a maturing industry, there is certainly no indications that the people within the industry have given up or intend to take it easy. The event really got started late Sunday when Laurie Balch, chief analyst for Gary Smith EDA, delivered her message. She said that the focus is becoming the verticals. "This change in focus is ... » read more

Shrink Or Package?
By Ed Sperling - 19 Jun, 2017 - Comments: 0

Advanced packaging is rapidly becoming a mainstream option for chipmakers as the cost of integrating heterogeneous components on a single die continues to rise. Despite several years of buzz around this shift, the reality is that it has taken more than a half-century to materialize. Advanced [getkc id="27" kc_name="packaging"] began with IBM flip chips in the 1960s, and it got another boost ... » read more

The Week In Review: Design
By Jesse Allen - 16 Jun, 2017 - Comments: 0

M&A Verific acquired Invionics' entire INVIO technology portfolio, adding a high-level scripting interface with 100 high-level APIs to its Parser Platform of approximately 2,000 low-level SystemVerilog and VHDL APIs. An R&D group from the company will also join Verific. Portable Stimulus An Early Adopter release of the Portable Stimulus specification has been made publicly availabl... » read more

Modeling On-Chip Variation At 10/7nm
By Ann Mutschler - 14 Jun, 2017 - Comments: 1

Simulation, a workhorse tool for semiconductor design, is running out of steam at 10/7nm. It is falling behind on chips with huge gate counts and an enormous number of possible interactions between all the different functions that are being crammed onto a die. At simulation's root is some form of SPICE, which has served as its underpinnings ever since SPICE was first published 44 years ago. ... » read more

Blog Review: June 14
By Jesse Allen - 14 Jun, 2017 - Comments: 0

In a video, Cadence's Tom Hackett looks at the evolving von Neumann computer architecture and the development of CCIX driven by recent cloud computing challenges. Mentor's Puneet Sinha notes it's been 17 years since the Toyota Prius went on sale worldwide, and looks ahead to the next 17 years of electric vehicles. Synopsys' Sri Deepti Pisipati gives an overview of the different topologies... » read more

The Week In Review: Design
By Jesse Allen - 09 Jun, 2017 - Comments: 1

Tools Mentor added new tools to its high-level synthesis portfolio. The DesignChecks tool helps find bugs during coding with a static mode that performs very fast linting-like checks of the code and a formal mode that uses a formal engine for a more exhaustive proof of issues. The synthesis-aware Coverage tool measures code coverage for C++ signoff and fast closure of synthesized RTL. It sup... » read more

Libraries: Standardization and Requirements For Power-Aware Dynamic Simulation
By Progyna Khondkar - 08 Jun, 2017 - Comments: 0

INTRODUCTION Multivoltage (MV) based power-aware (PA) design verification and implementation methodologies requires special power management attributes in libraries for standard, MV and Macro cells for two distinctive reason. The first aspect is to provide power and ground (also bias) supply or PG-pin information, which is mandatory for PA verification. The second reason is to provide a distin... » read more

Blog Review: June 7
By Jesse Allen - 07 Jun, 2017 - Comments: 0

Cadence's Paul McLellan listens in on Jeff Bier's Embedded Vision Summit keynote, where he argues the cost and power consumption of vision computing will decrease by about 1000X in the next three years. Synopsys' Sean Safarpour points to three reasons formal has grown in the last ten years to become a standard part of the verification toolbox. Mentor's Matthew Balance checks out the abili... » read more

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