tag: software

Challenges For A Post-Moore’s Law World
By Ed Sperling - 27 Jul, 2020 - Comments: 0

Semiconductor Engineering sat down to discuss challenges at the edge, the impact of open-source, and how to attract new talent, with Simon Segars, CEO of Arm; Joseph Sawicki, executive vice president of IC EDA at Mentor, a Siemens Business; Raik Brinkmann, CEO of OneSpin Solutions; Babak Taheri, CEO of Silvaco; John Kibarian, CEO of PDF Solutions; and Prakash Narain, CEO of Real Intent. The con... » read more

Rethinking Architectures Based On Power
By Ed Sperling - 13 Jul, 2020 - Comments: 0

The newest chips being developed for everything from the cloud to the edge of the network look nothing like designs of even a year or two ago. They are architected for speed, from the throughput of high-speed buses and external interconnects to the customized accelerators and arrays of redundant MACs. But many of these designs have barely scratched the surface for saving power, which will becom... » read more

The Increasingly Ordinary Task Of Verifying RISC-V
By Ann Mutschler - 03 Jun, 2020 - Comments: 0

As RISC-V processor development matures and its usage in SoCs and microcontrollers grows, engineering teams are starting to look beyond the challenges of the processor core itself. So far, the majority of industry verification efforts have focused on ISA compliance to standardize the RISC-V core. Now the focus is shifting to be how to handle verification as the system grows, especially as this... » read more

Practical Processor Verification
By Brian Bailey - 23 Apr, 2020 - Comments: 0

Custom processors are making a resurgence, spurred on by the early success of the RISC-V ISA and the ecosystem that is rapidly building around it. But this shift is amid questions about whether processor verification has become a lost art. Years ago custom processors were common. But as the market consolidated around a handful of companies, so did the tools and expertise needed to develop th... » read more

Using Processor Trace At The System Level
By Ann Mutschler - 23 Apr, 2020 - Comments: 0

The race to process more data faster using less power is creating a series of debug challenges at the system level, where developers need to be able to trace interactions across multiple and often heterogeneous processing elements that may function independently of each other. In general, trace is a hardware debug feature that allows the run-time behavior of IP to be monitored. More specific... » read more

Power Becomes Bigger Concern For Embedded Processors
By Ann Mutschler - 15 Apr, 2020 - Comments: 0

Power is emerging as the dominant concern for embedded processors even in applications where performance is billed as the top design criteria. This is happening regardless of the end application or the process node. In some high-performance applications, power density and thermal dissipation can limit how fast a processor can run. This is compounded by concerns about cyber and physical secur... » read more

Tracking Automotive’s Rapidly Shifting Ecosystem
By Ann Mutschler - 02 Apr, 2020 - Comments: 0

The automotive ecosystem is becoming much harder to navigate as automakers, Tier 1s and IP vendors redefine their relationships based upon shifting value caused by an rapidly expanding amount of increasingly interdependent and complex electronic content. Predictions of massive change started almost a decade ago with a number of pilot programs around autonomous vehicles. But those shifts real... » read more

More Multiply-Accumulate Operations Everywhere
By Ed Sperling - 02 Apr, 2020 - Comments: 1

Geoff Tate, CEO of Flex Logix, sat down with Semiconductor Engineering to talk about how to build programmable edge inferencing chips, embedded FPGAs, where the markets are developing for both, and how the picture will change over the next few years. SE: What do you have to think about when you're designing a programmable inferencing chip? Tate: With a traditional FPGA architecture you ha... » read more

Building Security IntoThe DevOps Life Cycle
By Synopsys - 01 Apr, 2020 - Comments: 0

The primary goal when breaking the build in the CI/CD DevOps life cycle is to treat security issues with the same level of importance as quality and business requirements. If quality or security tests fail, the continuous integration server breaks the build. When the build breaks, the CI/CD pipeline also breaks. Based on the reason for the broken build, appropriate activities such as archite... » read more

Software-Defined Hardware Gains Ground — Again
By Ann Mutschler - 26 Mar, 2020 - Comments: 0

The traditional approach of running generic software on x86-based CPUs is running out of steam for many applications due to the slowdown of Moore’s Law and the concurrent exponential growth in software application complexity and scale. In this environment, the software and hardware are disparate due the dominance of the x86 architecture. “The need for and advent of the hardware accelerat... » read more

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