Changes Ahead


With 3D stacked die looking increasingly promising, the question for much of the industry is exactly when this will happen, how it will happen, and what it will mean to the design process. To a large extent, in an attempt to buffer the risk, much of the fabless industry has been heading toward FPGA prototypes. It is uncertain whether that trend will continue at the same pace as 3D processes ... » read more

Turn Up The Heat


For the better part of two years talk of 3D stacking has been filled with concerns about thermal issues. If you stack logic on logic or memory on memory or CPU on CPU, the chance of causing a fatal failure in the circuitry was assumed to be very high. It turns out that may not be the case after all. Companies working with early prototypes of 3D stacks say silicon itself may be one of the bes... » read more

The Unifying Promise Of 3D


There’s been a lot of talk about 3D stacking lately. Mention it to any EDA vendor and they have plans in place. Mention it to large chipmakers and they’re already experimenting with it. And mention it to those several nodes behind and they’re ready to jump. Critics are quick to point out that all of these groups may not be talking about exactly the same thing. Slapping together two chi... » read more

3D Integration: Extending Moore’s Law Into The Next Decade


By Cheryl Ajluni At the 46th Design Automation Conference in San Francisco last month, attention turned to a discussion of how to extend the momentum of Moore’s Law into the next decade. One plausible solution, according to Philippe Magarshack, the general manager of Central CAD & Design Solutions at STMicroelectronics, is 3D stacking for complex System-on-Chips (SoCs). The concept of 3... » read more

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