tag: Synopsys

Getting Ready For An Efficient Shift To PCI Express 6.0 Designs With Optimized IP
By Gary Ruggles - 10 Jun, 2021 - Comments: 0

PCI Express (PCIe) 6.0 technology with key changes will bring about challenges that high-performance computing, artificial intelligence, and storage system-on-chip (SoC) designers will face. This article provides designers a summary of the major changes and how they can be handled to ensure a smooth and successful transition to PCIe 6.0. The three major changes in PCIe 6.0 that designers nee... » read more

Thermal Floorplanning For Chips
By Brian Bailey - 10 Jun, 2021 - Comments: 0

Heat management is becoming crucial to an increasing number of chips, and it's one of a growing number of interconnected factors that must be considered throughout the entire development flow. At the same time, design requirements are exacerbating thermal problems. Those designs either have to increase margins or become more intelligent about the way heat is generated, distributed, and dissi... » read more

Power, Performance — Avionics Designers Want It All
By Heidi Elliott - 10 Jun, 2021 - Comments: 0

Not long ago, the prevailing philosophy among chip designers for aviation systems could be summed up as, “I feel the need — the need for speed.” Today, aviation’s top guns have pulled back on the throttle a bit. There’s a more nuanced discussion balancing the need for performance versus power, with other factors coming into consideration such as safety, security certifications and ove... » read more

Blog Review: Jun 9
By Jesse Allen - 09 Jun, 2021 - Comments: 0

Arm's Partha Maji introduces a collaboration with the University of Cambridge to advance Bayesian statistics and probabilistic machine learning, which could play a vital role in safety-critical AI applications. Siemens' Thomas Dewey looks at a way to improve autonomous driving capabilities by enabling vehicles to train on past hazardous situations to provide and early warning for when they m... » read more

There’s More To Machine Learning Than CNNs
By Bryon Moyer - 09 Jun, 2021 - Comments: 1

Neural networks – and convolutional neural networks (CNNs) in particular – have received an abundance of attention over the last few years, but they're not the only useful machine-learning structures. There are numerous other ways for machines to learn how to solve problems, and there is room for alternative machine-learning structures. “Neural networks can do all this really comple... » read more

Reliability Costs Becoming Harder To Track
By SE Staff - 08 Jun, 2021 - Comments: 0

Ensuring reliability in chips is becoming more complex and significantly more expensive, shifting left into the design cycle and right into the field. But those costs also are becoming more difficult to define and track, varying greatly from one design to the next based upon process node, package technology, market segment, and which fab or OSAT is used. As the number of options increases fo... » read more

Is There a Practical Test For Rowhammer Vulnerability?
By Bryon Moyer - 08 Jun, 2021 - Comments: 3

Rowhammer is proving to be a difficult DRAM issue to fix. While efforts continue to mitigate or eliminate the effect, no solid solution has yet made it to volume production. In addition, more aggressive process nodes are expected to exacerbate the problem. In the absence of a fix, then, testing may be one way to give DRAM manufacturers and users some way to segregate devices that are more su... » read more

Digging Much Deeper With Unit Retest
By Anne Meixner - 08 Jun, 2021 - Comments: 0

Keeping test costs flat in the face of product complexity continues to challenge both product and test engineers. Increased data collection at package-level test and the ability to respond to it in a never-before level of detail has prompted device makers and assembly and test houses to tighten up their retest processes. Test metrology, socket contamination, and mechanical alignment have alw... » read more

Signal Connectivity Checks Are Not Just For Design-For-Test Teams
By Pawini Mahajan - 08 Jun, 2021 - Comments: 0

By Pawini Mahajan and Raja Koneru The complexity with system-on-chip (SoC) design continues to grow, creating greater complexity of the corresponding design-for-test (DFT) logic required for manufacturing tests. Design teams are challenged not only by high gate counts and the array of internally developed and third-party IP integrated into their designs: the need to achieve high-quality manu... » read more

The Next Generation of Testbench Debug Productivity
By Synopsys - 08 Jun, 2021 - Comments: 0

It is widely accepted that verification consumes at least sixty percent of time and resources on most semiconductor development projects. This statistic has been borne out by many industry surveys over the last twenty years. Verification technology has had to evolve to accommodate ever larger and more complex designs. Innovations such as constrained-random simulation and the Universal Verificat... » read more

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