tag: Synopsys

Blog Review: Dec. 30
By Jesse Allen - 30 Dec, 2020 - Comments: 0

Cadence's Paul McLellan considers what the next ten years will look like for the RISC-V ISA with an expanding software ecosystem and increasing number of commercial and open cores available. Siemens EDA's Harry Foster checks out the languages and libraries being used to design and verify FPGAs and how they've changed over the last several years. Synopsys' Jonathan Knudsen contends that IT... » read more

Why It’s So Hard To Stop Cyber Attacks On ICs
By Ed Sperling - 23 Dec, 2020 - Comments: 0

Semiconductor Engineering sat down to discuss security risks across multiple market segments with Helena Handschuh, security technologies fellow at Rambus; Mike Borza, principal security technologist for the Solutions Group at Synopsys; Steve Carlson, director of aerospace and defense solutions at Cadence; Alric Althoff, senior hardware security engineer at Tortuga Logic; and Joe Kiniry, princi... » read more

Blog Review: Dec. 23
By Jesse Allen - 23 Dec, 2020 - Comments: 0

Cadence's Paul McLellan checks out how Arm is becoming a powerhouse in the server and high-end space with the addition of new R&D and a focus on getting the most out of its architecture. Siemens EDA's Harry Foster continues his look at verification trends in FPGAs by checking out adoption of different simulation and formal technologies. Synopsys' Taylor Armerding looks ahead to 2021 w... » read more

RISC-V Verification Challenges Spread
By Ann Mutschler - 22 Dec, 2020 - Comments: 0

The RISC-V ecosystem is struggling to keep pace with rapid innovation and customization, which is increasing the amount of verification work required for each design and spreading that work out across more engineers at more companies. The historical assumption is that verification represents 60% to 80% or more of SoC project effort in terms of cost and time for a mature, mainstream processor... » read more

Stretching Engineers
By Brian Bailey - 22 Dec, 2020 - Comments: 1

Engineering has one constant — you innovate or fall by the wayside. That is true both for the things that are designed and for the engineers who design and build them. Today’s systems are putting new strains on engineers who can no longer be "tall and thin" or "short and fat." Those descriptions pertain to an engineer who is either highly specialized or one who has much broader experience. ... » read more

Multicore Debug Evolves To The System-Level
By Ann Mutschler - 22 Dec, 2020 - Comments: 0

The proliferation and expansion of multicore architectures is making debug much more difficult and time-consuming, which in turn is increasing demand for more comprehensive system-level tools and approaches. Multicore/multiprocessor designs are the most complex devices to debug. More interactions and interdependencies between cores mean more things possibly can go wrong. In fact, so many pro... » read more

5 Predictions For AI Innovation In 2021
By Arun Venkatachar - 22 Dec, 2020 - Comments: 0

By Arun Venkatachar and Stelios Diamantidis Artificial intelligence (AI) has emerged as one of the most important watchwords in all of technology. The once-utopian vision of developing machines that can think and behave like humans is becoming more of a reality as engineering innovations enable the performance required to process and interpret previously unimaginable amounts of data efficien... » read more

How 5G Is Influencing Silicon Design
By Synopsys - 21 Dec, 2020 - Comments: 0

5G is introducing a wide array of challenges in next-generation SoCs that go well beyond high bandwidth wireless. These include increasing system bandwidth, lowering SoC latency, and reducing power significantly for the connected internet of things. Using trusted standards-based IP and proven processing and analog IP at the most aggressive process technology nodes is needed to bring 5G to marke... » read more

Week In Review: Design, Low Power
By Jesse Allen - 18 Dec, 2020 - Comments: 0

Tools, Cloud, IP Valtrix Systems updated its STING design verification tool for RISC-V based CPU and SoC implementations. Version 1.9.0 adds support to verify recent changes to the RISC-V user and privilege specifications, including draft versions of the vector and bit manipulation standard extensions. Preliminary support for the draft version of the RISC-V hypervisor extension has also been a... » read more

Week In Review: Auto, Security, Pervasive Computing
By SE Staff - 18 Dec, 2020 - Comments: 0

Automotive Austin, Texas-based automotive startup Uhnder raised $45 million in Series C funding for its digital radar-on-chip. Telechips, a fabless semiconductor company that works on automotive SoCs, is using Arm’s IP to design its Dolphin5 SoC for ADAS (advanced drive assistance systems) and digital cockpits with in-vehicle infotainment (IVI). Dolphin5 will include the Arm’s Mali-G78A... » read more

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