tag: Synopsys

Blog Review: June 17
By Jesse Allen - 17 Jun, 2020 - Comments: 0

Mentor's Chris Spear provides an introduction to SystemVerilog Multidimensional Arrays and shares code samples to follow along. Cadence's Paul McLellan listens in on Sophie Wilson's 2020 Wheeler Lecture that traces the history of the microprocessor from the early days of Moore's Law through to increasing power and economic constraints that are causing a transition from general purpose to spe... » read more

Interconnect Challenges Grow, Tools Lag
By Brian Bailey - 15 Jun, 2020 - Comments: 2

Interconnects are becoming much more problematic as devices shrink and the amount of data being moved around a system continues to rise. This limitation has shown up several times in the past, and it's happening again today. But when the interconnect becomes an issue, it cannot be solved in the same way issues are solved for other aspects of a chip. Typically it results in disruption in how ... » read more

Week In Review: Design, Low Power
By Jesse Allen - 12 Jun, 2020 - Comments: 0

Synopsys acquired Qualtera, a provider of big data analytics for semiconductor test and manufacturing. Based in Montpellier, France and founded in 2010, Qualtera's Silicondash platform provides both off-line and in-line modules for data analytics, visualization, simulation, and modeling to allow for development of control strategies. Combined with Synopsys' TestMAX test automation solution, the... » read more

Week In Review: Auto, Security, Pervasive Computing
By SE Staff - 12 Jun, 2020 - Comments: 0

Edge, cloud, data center Programmable logic company Efinix used Cadence’s Digital Full Flow to finish Efinix’s Trion FPGA family for edge computing, AI/ML and vision processing applications, according to a press release. Last week Efinix also announced three software defined SoCs based on the RISC-V core. The SoCs are optimized to the Trion FPGAs. AI, machine learning Amazon will tempo... » read more

Essential DDR5 Features Designers Must Know
By Vadhiraj Sankaranarayanan - 11 Jun, 2020 - Comments: 2

JEDEC has defined and developed three DDR standards – standard DDR, mobile DDR, and graphic DDR – to help designers meet their memory requirements. DDR5 will support a higher data rate (up to 6400 Mb/s) at a lower I/O Voltage (1.1V) and a higher density (based on 16Gb DRAM dies) than DDR4. DDR5 DRAMs and dual-inline memory modules (DIMMs) are expected to hit the market in 2020. This article... » read more

Aging Problems At 5nm And Below
By Brian Bailey - 11 Jun, 2020 - Comments: 3

The mechanisms that cause aging in semiconductors have been known for a long time, but the concept did not concern most people because the expected lifetime of parts was far longer than their intended deployment in the field. In a short period of time, all of that has changed. As device geometries have become smaller, the issue has become more significant. At 5nm, it becomes an essential par... » read more

ESD Requirements Are Changing
By Bryon Moyer - 11 Jun, 2020 - Comments: 1

Standards for specifying a chip’s ability to withstand electrostatic discharge (ESD) are changing – in some cases, getting tougher, and in others, easing up. ESD protection has been on a path from a one-size-fits-all approach to one where a signal’s usage helps to determine what kind of protection it should get. Protecting chips from ESD damage has been a longstanding part of IC design... » read more

Fundamental Changes In Economics Of Chip Security
By Ed Sperling - 10 Jun, 2020 - Comments: 0

Protecting chips from cyberattacks is becoming more difficult, more expensive and much more resource-intensive, but it also is becoming increasingly necessary as some of those chips end up in mission-critical servers and in safety-critical applications such as automotive. Security has been on the semiconductor industry's radar for at least the past several years, despite spotty progress and ... » read more

Blog Review: June 10
By Jesse Allen - 10 Jun, 2020 - Comments: 0

Cadence's Paul McLellan considers the issues around benchmarking neural networks running on different hardware and challenges in comparing designs. Mentor's Shivani Joshi points to a few of the different types of jitter and some key factors to review when trying to limit jitter. Synopsys' Fred Bals notes that while the National Vulnerability Database is a good source for information on public... » read more

Configuring Processors In The Field
By Brian Bailey - 08 Jun, 2020 - Comments: 0

The convergence of two technologies, extensible processors and embedded FPGAs, is enabling the creation of processors that can be dynamically configured in the field. But it's not clear if there is a need for them or how difficult would it be to program them. This remains an open question even though there is evidence of its usefulness in the past and new products are expected to reach the mark... » read more

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