tag: Synopsys

Blog Review: Mar. 20
By Jesse Allen - 20 Mar, 2019 - Comments: 0

Cadence's Paul McLellan argues that rapid improvements in the performance of general-purpose computing led to a lack of innovation in domain-specific architectures, but as scaling slows, they're entering a new golden age. In a video, Mentor's Colin Walls takes a look at the use of floating point in an embedded application and some of the pitfalls associated with it. Synopsys' Taylor Armer... » read more

Week in Review: IoT, Security, Auto
By Jeff Dorsch - 15 Mar, 2019 - Comments: 0

Internet of Things Apple purchased a portfolio of eight granted and pending patents that belonged to Lighthouse AI, a smart home security camera startup that ceased operations near the end of 2018. The portfolio was acquired at about the same time, according to the U.S. Patent & Trademark Office; financial terms weren’t revealed. Also not disclosed, as usual, is what Apple will do with t... » read more

Week In Review: Design, Low Power
By Jesse Allen - 15 Mar, 2019 - Comments: 0

M&A Nvidia will acquire Mellanox for $6.9 billion in cash, the largest deal in the chipmaker's history. Traditionally a PC GPU company, Nvidia has made a push into high-performance computing, particularly for AI workloads. Founded in 1999, Israel-based Mellanox focuses on end-to-end Ethernet and InfiniBand interconnect solutions and services for servers and storage. According to Nvidia, Me... » read more

Using Less Power At The Same Node
By Brian Bailey - 14 Mar, 2019 - Comments: 0

Going to the next node has been the most effective way to reduce power, but that is no longer true or desirable for a growing percentage of the semiconductor industry. So the big question now is how to reduce power while maintaining the same node size. After understanding how the power is used, both chip designers and fabs have techniques available to reduce power consumption. Fabs are makin... » read more

Memory Tradeoffs Intensify in AI, Automotive Applications
By Ann Mutschler - 14 Mar, 2019 - Comments: 0

The push to do more processing at the edge is putting a strain on memory design, use models and configurations, leading to some complex tradeoffs in designs across a variety of markets. The problem is these architectures are evolving alongside these new markets, and it isn't always clear how data will move across these chips, between devices, and between systems. Chip architectures are becom... » read more

The Importance Of Using The Right DDR SDRAM Memory
By Vadhiraj Sankaranarayanan - 14 Mar, 2019 - Comments: 0

Selecting the right memory technology is often the most critical decision for achieving the optimal system performance. Designers continue to add more cores and functionality to their SoCs; however, increasing performance while keeping power consumption low and silicon footprint small remains a vital goal. DDR SDRAMs, DRAMs in short, meet these memory requirements by offering a dense, high-perf... » read more

Accelerating Toshiba’s SoC Design with Fusion Compiler
By Synopsys - 13 Mar, 2019 - Comments: 0

This white paper discusses how Toshiba and Synopsys worked closely to bring-up Fusion Compiler and deploy it throughout Toshiba's advanced proprietary Tachyon Design System. With improved power, performance, and area (PPA), faster time-to-results and a predictable design flow have been validated on the latest, differentiated automotive SoC ASIC products, and Fusion Compiler is being broadly dep... » read more

Blog Review: Mar. 13
By Jesse Allen - 13 Mar, 2019 - Comments: 0

Mentor's Tom Fitzpatrick questions whether deep learning approaches can really help improve coverage in modern, complex designs. Cadence's Paul McLellan listens in at MWC as Huawei chairman Guo Ping defends the company's security practices and shows where its heading in 5G. Synopsys' Eric Huang checks out the newly announced USB4 specification, changes to previous USB names, and a few things ... » read more

Domain Expertise Becoming Essential For Analytics
By Ed Sperling - 12 Mar, 2019 - Comments: 0

Sensors are being added into everything, from end devices to the equipment used to make those sensors, but the data being generated has limited or no value unless it's accompanied by domain expertise. There are two main problems. One is how and where to process the vast amount of data being generated. Chip and system architectures are being revamped to pre-process more of that data closer to... » read more

Designing An AI SoC
By Ed Sperling - 11 Mar, 2019 - Comments: 0

Susheel Tadikonda, vice president of networking and storage at Synopsys, looks at how to achieve economies of scale in AI chips and where the common elements are across all the different architectures. https://youtu.be/fm0kxnj3DuM » read more

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