The Week In Review: Design


Numbers EDA and IP sales increased 5.6% in Q2 to $2.013 billion, up from $1.907 billion in the same period in 2015, according to the most recent Electronic System Design Alliance numbers. Asia/Pacific revenue increased 10.9% to $608.1 million; Japan increased 15.7% to $211.4 million. The Americas increased 4.4% to $908.4 million. IP Cadence launched the latest generation of its Xtensa ... » read more

Building Chips That Can Learn


The idea that devices can learn optimal behavior rather than relying on more generalized hardware and software is driving a resurgence in artificial intelligence, machine leaning, and cognitive computing. But architecting, building and testing these kinds of systems will require broad changes that ultimately could impact the entire semiconductor ecosystem. Many of these changes are wel... » read more

Team Work


While I am not much of a golf player, I participated in a golf tournament over the summer. It was a very friendly setup with teams of four playing against each other. Each player of the team hits his ball, and the ball that lands in the best position determines the starting point for every one of the team for the next stroke. The fact that only the best shot of the team counts, definitely ma... » read more

Development Testing For C# Applications


Static analysis shouldn’t be about finding loads of coding style or standard issues. It should be focused on finding the most critical defects. Although traditional byte code analysis solutions such as FxCop are useful, they can miss critical, crash causing defects - plus produce a large set of coding style issues, which can slow down the development team. Learn how the Coverity Development T... » read more

Blog Review: Sept. 28


Cadence's Paul McLellan provides a glimpse of TSMC's roadmap, including what to look for at 7nm, low-power processes, and the ecosystem around the process. Mentor's Stephen Pateras notes that throughout the evolution of DFT, two rules for success have persisted. Early analysis suggests the largest DDoS attack in history, targeted at security reporter Brian Krebs, may have leveraged flaws ... » read more

The Week In Review: Design


Tools Real Intent updated its Ascent Lint product, adding 50 new customer-driven rules, improved support of VHDL and System Verilog, and a new database-driven debugger with an integrated source browser and improved schematic visualization. IP ARM launched a new real-time processor with advanced safety features for autonomous vehicles and medical and industrial robots. The processor, Co... » read more

Blog Review: Sept. 21


Mentor's Ricardo Anguiano takes a look at a proposal to prevent auto accidents from becoming pile-ups: the relaying of hazard information to the cloud and on to upcoming vehicles. Why get rid of 3.5mm audio jacks? Synopsys' Michael Posner says it's all about the power optimization in the upcoming USB Type-C digital audio specification. NXP's Anand Kannan also thinks Type-C should be the d... » read more

Plugging Holes In Machine Learning


The number of companies using machine learning is accelerating, but so far there are no tools to validate, verify and debug these systems. That presents a problem for the chipmakers and systems companies that increasingly rely on machine learning to optimize their technology because, at least for now, it creates the potential for errors that are extremely difficult to trace and fix. At the s... » read more

The Week In Review: IoT


Deals Verizon Communications agreed to acquire Sensity Systems of Sunnyvale, Calif., a supplier of energy-efficient light-emitting diode lighting equipment to serve as the foundation for its Internet of Things platform for smart cities; financial terms weren’t disclosed. The transaction is expected to close in the fourth quarter. Mike Lanman, Verizon’s senior vice president of Enterprise P... » read more

The Week In Review: Design


IP Sonics unveiled Energy Processing Unit (EPU) IP, based on the company's ICE-Grain power architecture, to better manage and control circuit idle time. The IP facilitates design of SoC power architecture and implementation and verification of the resulting power management subsystem. Synopsys debuted ARC SEM security processors with timing and power randomization features to protect agai... » read more

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