tag: Synopsys

Reaching The Power Budget
By Ann Mutschler - 11 Aug, 2016 - Comments: 1

Everything related to power in chip design today is a big deal—and it’s just getting bigger. Meeting the power budget is becoming harder at each new node, but it's also becoming difficult in a number of new application areas at existing nodes. That's a big problem because [getkc id="108" kc_name="power"] is now considered a competitive advantage in many markets. It's also one of the most... » read more

Blog Review: Aug. 10
By Jesse Allen - 10 Aug, 2016 - Comments: 0

Is the end near for FinFETs? Applied's Mike Chudzik digs into the impact of rising parasitic resistance and parasitic capacitance and the challenges of scaling to 5nm. Cadence's Paul McLellan checks out the method UC Berkeley is using to build RISC-V processors. Mentor's Colin Walls warns that in C even the simplest things, like the declaration of variables, have pitfalls for the unwary. ... » read more

Power Hungry?
By Synopsys - 10 Aug, 2016 - Comments: 0

Rapid changes in SoC power issues have forced a rethinking of methodologies throughout the design flow to account for power-related effects. At 65 nanometer process nodes and below, leakage power and dynamic power consumption make it increasingly difficult to meet power budgets. Achieving timing and signal integrity closure is now tightly coupled with power optimization and power net distributi... » read more

Is Security A Priority?
By Ed Sperling - 10 Aug, 2016 - Comments: 0

Ask any two executives in the semiconductor industry about security threats and there is a good chance you will get two totally different answers. The disturbing part is they both may be right. In markets where there is no physical danger to people, security always has been viewed a risk versus profit equation. At conferences over the past year, numerous executives have touted the Transport... » read more

What’s Important For IoT—Power, Performance Or Integration?
By Ed Sperling - 04 Aug, 2016 - Comments: 0

Semiconductor Engineering sat down with Steve Hardin, director of product development for AT&T's IoT Solutions Group; Wayne Dai, CEO of VeriSilicon; John Koeter, vice president of the Solutions Group at [getentity id="22035" e_name="Synopsys"]; and Rajeev Rajan, vice president for IoT at [getentity id="22819" comment="GlobalFoundries"]. What follows are excerpts of that conversation. SE:... » read more

Blog Review: Aug. 3
By Jesse Allen - 03 Aug, 2016 - Comments: 0

Mentor's Andrew Macleod presents three hours of highlights from this year's IESF automotive conference in Detroit with topics from making cars more affordable to reaching an efficiency of 54.5 MPG. Cadence's Paul McLellan checks out the state of the smartphone landscape now that consolidation in the market seems to be complete at the Linley Mobile Conference. Synopsys' Eric Huang consider... » read more

Mixed-signal/Low-power Design
By Jeff Dorsch - 03 Aug, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss mixed-signal/low-power IC design with Phil Matthews, director of engineering at Silicon Labs; Yanning Lu, director of analog IC design at Ambiq Micro; Krishna Balachandran, director of low power solutions marketing at [getentity id="22032" comment="Cadence"]; Geoffrey Ying, director of product marketing, AMS Group, [getentity id="22035" e_name="Syno... » read more

What’s Holding Back Analog?
By Ann Mutschler - 01 Aug, 2016 - Comments: 2

The uneasy relationship between digital and analog, coupled with tools that are either ineffective or outright ignored by the analog community, may be limiting the growth potential and technological advances in that market. That certainly doesn’t mean analog isn’t growing. In fact, analog is an increasingly critical component of ICs and the electronic devices they inhabit. The global ele... » read more

The Week In Review: Design
By Jesse Allen - 29 Jul, 2016 - Comments: 0

IP Rambus debuted 3200 Mbps DDR4 PHY, targeted at the data center and networking markets, on the GlobalFoundries FX-14 ASIC platform using the company's 14nm Power Plus (LPP) process. The PHY is DFI 4.0 compatible, and supports 16 – 72-bit interfaces, along with single and multi-rank configurations. Synopsys introduced VIP and UVM source code test suite for Ethernet 200G, supporting 4x5... » read more

Time For A DDR Background Check
By Pat Sheridan - 28 Jul, 2016 - Comments: 0

In this month’s blog we continue our discussion of power management, specifically looking at how architects can improve the energy efficiency of their SoC as it uses system memory. In March we teamed up with Micron, a global supplier of high performance, low power memory technologies, to present a tutorial at SNUG Silicon Valley (see proceedings) explaining the practical steps system desig... » read more

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