tag: Synopsys

New Drivers For Test
By Brian Bailey - 28 Jul, 2016 - Comments: 0

Mention Design for Test (DFT) and scan chains come to mind, but there is much more to it than that—and the rules of the game are changing. New application areas such as automotive may breathe new life into built-in self-test (BIST) solutions, which could also be used for manufacturing test. So could DFT as we know it be a thing of the past? Or will it continue to have a role to play? Te... » read more

Speeding Up The Design Process
By Ed Sperling - 28 Jul, 2016 - Comments: 0

A rush to plant a stake in new markets, coupled with uncertainty about how to generate a reasonable return on investment in those markets, is ratcheting up pressure on chipmakers. They now must come up with more customized solutions in less time, frequently in smaller volumes, and with the ability to modify them in shorter time spans if market opportunities shift in unexpected ways. This aff... » read more

IC Validator Programmable EERC Netlist Domain Checking Technology
By Synopsys - 27 Jul, 2016 - Comments: 0

Traditional visual inspection or manual checking for electrical rule compliance is both time consuming and error prone. A new, comprehensive reliability solution is needed to reduce time to market, improve reliability and ensure longer device operation. This paper introduces IC Validator programmable Extended Electrical Rule Checking (EERC) and categorizes electrical rule checking (ERC) into th... » read more

Blog Review: July 27
By Jesse Allen - 27 Jul, 2016 - Comments: 0

Mentor's Tom Fitzpatrick investigates how to add new behavior to an existing testbench with the UVM factory class. Synopsys' Srinivas Vijayaragavan and Pooja Gupta dig into new features of SAS 24G, including how its effective speed was doubled to 24G though signaling rate remains at 22.5G. Cadence's Paul McLellan highlights a presentation from the SEMI/Gartner Market Symposium focused on ... » read more

How Cache Coherency Impacts Power, Performance
By Ann Mutschler - 27 Jul, 2016 - Comments: 0

As discussed in part one, one of the reasons cache coherency is becoming more important is the shared common memory resource in designs today. Various agents in the design want to access the data the fastest they can, putting pressure on the CPU complex to manage all of the requests. Until a generation ago, it was okay for the CPU to control that memory and have access to it, as well as be t... » read more

Mixed-signal/Low-power Design
By Jeff Dorsch - 26 Jul, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss mixed-signal/low-power IC design with Phil Matthews, director of engineering at Silicon Labs; Yanning Lu, director of analog IC design at Ambiq Micro; Krishna Balachandran, director of low power solutions marketing at [getentity id="22032" comment="Cadence"]; Geoffrey Ying, director of product marketing, AMS Group, [getentity id="22035" e_name="Syno... » read more

Getting The Jump On Analog/RF IP
By Ed Sperling - 26 Jul, 2016 - Comments: 0

When Magma Design was sold to Synopsys in 2012, then-president and COO Roy Jewell sat down with VC Lucio Lanza to figure out what to do next. As Jewell tells it, Lanza convinced him not to take another job. While it’s too early to tell if that was sage advice, it did trigger a search for a new business and a way of funding it. Jewell said that when Magma went looking for money, it raised $... » read more

Introduction to the Compute Express Link Standard
By Synopsys - 24 Jul, 2016 - Comments: 0

By Gary Ruggles, Sr. Product Marketing Manager, Synopsys Compute Express Link (CXL), a new open interconnect standard, targets intensive workloads for CPUs and purpose-built accelerators where efficient, coherent memory access between a Host and Device is required. A consortium to enable this new standard was recently announced simultaneously with the release of the CXL 1.0 specification. Th... » read more

The Week In Review: Design
By Jesse Allen - 22 Jul, 2016 - Comments: 0

Tools Synopsys updated its static timing analysis tool to use smart engineering change order (ECO) technology, which the company says reduces memory requirements by 5X and speeds runtime by 2X. The release also allows more scenarios on a single server, or flexible distribution to take advantage of customers' private compute clouds. IP Synopsys released MIPI display and camera interface... » read more

To 7nm And Beyond
By Ed Sperling - 21 Jul, 2016 - Comments: 4

Gary Patton, chief technology officer at [getentity id="22819" comment="GlobalFoundries"], and Thomas Caulfield, senior vice president and general manager of Fab 8, sat down with Semiconductor Engineering to discuss future directions in technology, including the next rev of FD-SOI, the future of Moore’s Law, and how some very public challenges will likely unfold. SE: What do you see as the... » read more

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