tag: Synopsys

Powerful Software Optimization
By Brian Bailey - 05 Dec, 2013 - Comments: 0

It is commonly accepted that the higher you go in the design chain, the bigger the impact that design and implementation decision can have. While power optimization may have started deep in the silicon, the success of a product, such a smart phone, often is based on the time between charges. Batteries provide a finite energy resource, and while low-level optimization may focus on power reductio... » read more

Blog Review: Dec. 4
By Ed Sperling - 04 Dec, 2013 - Comments: 0

Mentor’s Harry Foster closes his epic study on functional verification with an interesting insight about the real value of industry studies—new questions. It’s hard to argue with that. Cadence’s Brian Fuller takes a shot at the people taking shots at Amazon’s drone delivery service (the term du jour is robots). It does sound cool, as long as they don’t deliver the kind of payloa... » read more

The Rise Of Semiconductor IP Subsystems
By Various Writers - 04 Dec, 2013 - Comments: 0

The semiconductor IP (SIP) market arose when SIP vendors created IP functions that mirrored those found in the discrete semiconductor market and made those functions available to SoC designers in the form of hard or soft SIP blocks. As the SoC and SIP markets evolved, it was a natural evolution that many discrete SIP functions be converged into larger blocks that mimic system-level functions (i... » read more

The Week In Review: System-Level Design
By Ed Sperling - 27 Nov, 2013 - Comments: 0

Synopsys won a deal with Germany’s Hyperstone, which will use Synopsys verification tools for SoCs in industrial, automotive and medical applications. As SoCs used in industrial and “safety-critical” markets grow in complexity and move to more advanced process nodes, more advanced tools also are necessary. Si2 uncorked a new release of its OpenAccess scripting interface—oaScript Exte... » read more

Blog Review: Nov. 27
By Ed Sperling - 27 Nov, 2013 - Comments: 0

Synopsys’ Brent Gregory is looking at real-world experiments to figure out which EDA software is better. Make sure to check out his stats. Cadence’s Brian Fuller interviews two Samsung engineers in a video about the image technology in smart phone cameras and just how far it’s progressed. Hint: Don’t forget to charge your phone on your next vacation. Mentor’s Colin Walls points ... » read more

The Week In Review: System-Level Design
By Ed Sperling - 22 Nov, 2013 - Comments: 0

Synopsys rolled out new non-volatile memory IP that cuts power by 90% and reduces area in half. The company said it accomplished this feat with a single-bit read capability, which can drop read operation down to 0.9 volts and peak current to less than 10 microamps during erase and programming. The target of the ultra-low power IP is RFID and near-field computing ICs. Mentor Graphics posted p... » read more

Even Standard IP Isn’t Always Standard
By Ed Sperling - 21 Nov, 2013 - Comments: 0

Time to market and rising complexity are forcing the use of more third-party IP as well as increasing reuse of internally developed IP. But as more IP is added into SoCs, chipmakers are discovering some interesting things: Not all IP works together as planned, even when it’s well characterized. As with cars, performance and mileage vary greatly depending upon who’s driving—and who’s... » read more

Where Dragons Roam
By Tom De Schutter - 21 Nov, 2013 - Comments: 0

For more than half a year now, I am living with two dragons at home. Luckily from the outside they look just like regular children, so we didn’t have to upgrade our house. But we have to remind our little dragons to switch to human languages when they talk to us. It is interesting, and also a bit sad, to realize that as we “grow up,” we lose the ability to let our imagination go wild a... » read more

Stacked Die Moves From Drawing Board To Reality
By Ed Sperling - 21 Nov, 2013 - Comments: 0

After decades of moving in a straight line from one process geometry shrink to the next, much of the semiconductor industry has taken a step back to figure out what comes next. While companies such as Intel, IBM and Samsung continue to look as far ahead as the 3nm process node, along with new materials to improve electron mobility and new transistor designs based on electron tunneling and carbo... » read more

Verifying Cache Coherency Protocols With Verification IP
By Various Writers - 21 Nov, 2013 - Comments: 0

The use of on-chip cache memory helps design teams optimize multicore designs for both power and performance. While the use of hardware to implement cache coherency enables design teams to improve SoC performance, it adds significantly to verification complexity. The use of verification IP (VIP) enables engineers to validate such designs, although the VIP's effectiveness depends on its advanced... » read more

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