tag: Synopsys

The Trouble With Semiconductor IP
By Ed Sperling - 01 Dec, 2010 - Comments: 0

Low-Power Engineering takes a poll of the big problem with IP and how to solve it from Ken Brock, senior staff product marketing manager at Synopsys; Kalar Rajendiran, senior director of marketing at eSilicon; Mike Gianfagna, vice president of marketing at Atrenta, and Jim McCanny, CEO of Altos Design. [youtube vid=b7wnkY_rU04] » read more

Silence Is Golden
By Ann Mutschler - 01 Dec, 2010 - Comments: 0

As the industry continues to march along building devices with ever-increasing battery life, it is necessary to migrate to the latest and greatest process nodes, which as we all know are smaller and use lower voltages. However, any noise in the system—whether it was there before or you start to use something like USB 3.0 or SATA or something else—is actually going to increase the number of ... » read more

Building Up In 3D
By Ed Sperling - 18 Nov, 2010 - Comments: 0

By Ed Sperling Stacked die are expected to begin showing up in volume in late 2012 and in 2013, turning what has been a science experiment into a mainstream way of designing and manufacturing SoCs. This magnitude of this shift cannot be overstated, and clearly all of the pieces are not in place to make it all happen immediately. There also are significant technology challenges to overcome, ... » read more

Verifying At The System Level
By Ed Sperling - 18 Nov, 2010 - Comments: 0

By Ed Sperling Verification has always been the problem child of SoC design. It requires the most engineering resources, the largest block of time and the biggest budget in the design process. And at each new process node the problem gets bigger, in part because there is more stuff on each die—transistors, memory, interconnects, I/O, functionality—and in part because chipmakers are being c... » read more

ARM’s Race
By Ed Sperling - 05 Nov, 2010 - Comments: 0

Prior to the Synopsys acquisition of Virage Logic, Synopsys seemed to have an almost exclusive relationship with ARM. Since then, Cadence and Mentor Graphics have both been cutting deals with ARM for support of its IP cores. What’s changed? With regard to the Virage Logic acquisition, very little. Synopsys did acquire the ARC processor through that deal, but ARC had been much more focused ... » read more

The Trouble With Low-Power Verification
By Ed Sperling - 04 Nov, 2010 - Comments: 0

By Ed Sperling If verification accounts for 70% of the non-recurring engineering expenses in a design, what percentage does verifying a low-power design actually consume? Answer: No one knows for sure. The reason has more to do with insufficient data than tools, processes or flows. That’s also the reason that power models have never been created for more than a single design. “Power... » read more

How Software Utilizes Cores
By Ed Sperling - 04 Nov, 2010 - Comments: 2

By Ann Steffora Mutschler When writing software, how does the design engineer determine how much power it will draw on a particular targeted platform? While the question seems straightforward, the answer is not. The industry is just starting to develop the ability to get some data in that space, according to Cary Chin, director of technical marketing for Synopsys’ low-power solutions gr... » read more

Making Software More Efficient
By Ed Sperling - 04 Nov, 2010 - Comments: 0

By Ed Sperling Software is being targeted by most of the major chip vendors and EDA companies as the next big opportunity for saving power, but exactly which software should be modified and by whom isn’t always clear. To some extent those answers depend upon which part of the software stack vendors or engineers believe can be adjusted most easily, and so far there is no widespread agreeme... » read more

Experts At The Table: Timing Constraints
By Ed Sperling - 22 Oct, 2010 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to discuss timing constraints with ARM Fellow David Flynn; Robert Hoogenstryd, director of marketing for design analysis and signoff at Synopsys; Michael Carrell, product marketing for front end design at Cadence; Ron Craig, senior marketing manager at Atrenta; and Himanshu Bhatnagar, executive director of VLSI design at Mindspeed Technologies. Wh... » read more

Best Practices For Multicore SoC Test And Debug
By Ann Mutschler - 21 Oct, 2010 - Comments: 0

By Ann Steffora Mutschler In increasingly complex SoC designs, many of which contain multiple cores and multiple modes, determining best practices for testing and debugging is a moving target. Jason Andrews, architect at Cadence Design Systems, said multicore debug is a huge issue. It isn’t easy to do, and there aren’t many good ways to do it. He suggested one approach is to try to u... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy