Planning EDA’s Next Steps


Anirudh Devgan, Cadence's new CEO, and the recipient of the Phil Kaufman Award in December, sat down with Semiconductor Engineering to talk about what's next in EDA, the underlying technology and business challenges and changes, and new markets that are unfolding for floor-planning, verification, CFD, and advanced packaging. SE: Where does EDA need to improve? Devgan: We have made it much... » read more

Chiplets Enter The Supercomputer Race


Several entities from various nations are racing each other to deliver and deploy chiplet-based exascale supercomputers, a new class of systems that are 1,000x faster than today’s supercomputers. The latest exascale supercomputer CPU and GPU designs mix and match complex dies in advanced packages, adding a new level of flexibility and customization for supercomputers. For years, various na... » read more

Week In Review: Manufacturing, Test


Packaging ASE, AMD, Arm, Google, Intel, Meta, Microsoft, Qualcomm, Samsung, and TSMC have announced the formation of a consortium that will establish a die-to-die interconnect standard and foster an open chiplet ecosystem. The founding companies also ratified the UCIe specification, an open industry standard developed to establish a standard interconnect at the package level. The UCIe 1.0 s... » read more

Week In Review: Design, Low Power


Tools & IP Imperas Software introduced the RISC-V Verification Interface (RVVI). The open standard and methodology can be adapted to any configuration permitted within the RISC-V specifications. RVVI defines interfaces between RTL, reference model, and testbench for RISC-V design verification, with the aim of making RISC-V processor DV reusable. It supports multi-hart, superscalar, and out... » read more

2D Semiconductors Make Progress, But Slowly


Researchers are looking at a variety of new materials at future nodes, but progress remains slow. In recent years, 2D semiconductors have emerged as a leading potential solution to the problem of channel control in highly scaled transistors. As devices shrink, the channel thickness should shrink proportionally. Otherwise, the gate capacitance won’t be large enough to control the flow of cu... » read more

Data Center Architectures In Flux


Data center architectures are becoming increasingly customized and heterogeneous, shifting from processors made by a single vendor to a mix of processors and accelerators made by multiple vendors — including system companies' own design teams. Hyperscaler data centers have been migrating toward increasingly heterogeneous architectures for the past half decade or so, spurred by the rising c... » read more

Transistors Reach Tipping Point At 3nm


The semiconductor industry is making its first major change in a new transistor type in more than a decade, moving toward a next-generation structure called gate-all-around (GAA) FETs. Although GAA transistors have yet to ship, many industry experts are wondering how long this technology will deliver — and what new architecture will take over from there. Barring major delays, today’s GAA... » read more

2022 Chip Forecast: Mixed Signals


Jim Feldhan, president of Semico Research, sat down with Semiconductor Engineering to talk about the outlook for the semiconductor market. SE: What was your final 2021 semiconductor forecast? What is your 2022 semiconductor forecast? Feldhan: For 2021, world semiconductor revenues totaled $558 billion and units totaled over 1.1 trillion units. In terms of growth rate, revenues increased 2... » read more

Week In Review: Manufacturing, Test


Chipmakers Intel has announced a definitive agreement to acquire Tower, a specialty foundry vendor, for approximately $5.4 billion. With the acquisition of Tower, Intel expands its efforts in the foundry business, and put its rivals on notice. With Tower, Intel gains access to mature processes as well as specialty technologies, such as analog, CMOS image sensor, MEMS, power management and RF. ... » read more

Week In Review: Manufacturing, Test


Fab tools Lam Research has rolled out a new suite of selective etch products for use in developing next-generation technologies, such as gate-all-around (GAA) transistors. In the fab, selective etch helps chipmakers with complex structures. These etch tools provide selective and precision etching without modifying or causing damage to other critical material layers. Composed of three new... » read more

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