To 10nm And Beyond


Hong Hao, senior vice president of the foundry business at Samsung Semiconductor, sat down with Semiconductor Engineering to discuss the future direction of transistors, process technology, lithography and other topics. What follows are excerpts of those conversations. SE: Samsung recently rolled out its 10nm finFET technology. It appears that Samsung is the world’s first company to ship 1... » read more

Closing The Power Integrity Gap


Voltage drop has always been a significant challenge. As far back as 130nm, specialist tools were being used to ensure that enough local decoupling capacitance (decap) cells were inserted in addition to larger decaps implemented around the SoC. But advanced nodes are complicating matters and further increasing complexity. These technological challenges, which underlie the power, performance ... » read more

10nm FinFET Market Heats Up


The 10nm finFET market is heating up in the foundry business amid the ongoing push to develop chips at advanced nodes. Not long ago, Intel announced its 10nm finFET process, with plans to ramp up the technology in 2017. Then, TSMC recently introduced its 10nm process, with plans to move into production by the fourth quarter of 2016. Now, Samsung Electronics said that it has commenced mass... » read more

The Week In Review: Manufacturing


Chipmakers Alain Kaloyeros, president of SUNY Polytechnic Institute, has resigned. This comes amid charges that Kaloyeros was involved in an alleged bid-rigging scheme, according to multiple reports. SUNY Poly, a high-tech educational ecosystem in New York, was recently formed from the merger of the SUNY College of Nanoscale Science and Engineering (CNSE) and the SUNY Institute of Technology. ... » read more

Early Power Modeling Using SystemC And TSMC System-PPA


Power consumption is often more important than performance in today’s SoC designs because of battery size and power dissipation limitations. The dilemma is that the most leverage available to optimize power consumption is at the architectural design stage, but there often is not enough information available early enough to make accurate power decisions. On the performance side, SystemC mod... » read more

The Week In Review: Manufacturing


Chipmakers In 2016, growth in the pure-play foundry business will be driven by leading-edge processes, according to IC Insights. In fact, the increase in pure-play foundry sales this year is forecast to be almost entirely due to processes at » read more

The Week In Review: Design


Numbers EDA and IP sales increased 5.6% in Q2 to $2.013 billion, up from $1.907 billion in the same period in 2015, according to the most recent Electronic System Design Alliance numbers. Asia/Pacific revenue increased 10.9% to $608.1 million; Japan increased 15.7% to $211.4 million. The Americas increased 4.4% to $908.4 million. IP Cadence launched the latest generation of its Xtensa ... » read more

TSMC OIP, Vertical Integration And The Power of Ecosystems


After several attempts I’ve made it – my presentation at the TSMC OIP Ecosystem Forum was accepted this year. You may ask, what does a front-end guy like me do at a technology implementation forum like TSMC OIP? And why is he excited about it? The short answer is that it brings back my past. I am excited about how the front-end flows and implementation flows get connected in a closer way. I... » read more

Blog Review: Sept. 28


Cadence's Paul McLellan provides a glimpse of TSMC's roadmap, including what to look for at 7nm, low-power processes, and the ecosystem around the process. Mentor's Stephen Pateras notes that throughout the evolution of DFT, two rules for success have persisted. Early analysis suggests the largest DDoS attack in history, targeted at security reporter Brian Krebs, may have leveraged flaws ... » read more

Packaging Wars Begin


The advanced IC-packaging market is turning into a high-stakes competitive battleground, as vendors ramp up the next wave of [getkc id="82" kc_name="2.5D"]/[getkc id="42" kc_name="3D"] technologies, high-density fan-out packages and others. At one time, the outsourced semiconductor assembly and test ([getkc id="83" comment="OSAT"]) vendors dominated and handled the chip-packaging requirement... » read more

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