tag: UltraSoC

Week In Review: Design, Low Power
By Jesse Allen - 28 Jun, 2019 - Comments: 0

VESA published the DisplayPort 2.0 standard, which allows for a max payload of 77.37 Gbps, a 3X increase in data bandwidth performance compared to DisplayPort 1.4a. The latest release also includes capabilities to address beyond 8K resolutions, higher refresh rates and HDR support at higher resolutions, multiple display configurations, and support for 4K-and-beyond VR resolutions. It is backwar... » read more

Test Chips Play Larger Role At Advanced Nodes
By Ann Mutschler - 27 Jun, 2019 - Comments: 0

Test chips are becoming more widespread and more complex at advanced process nodes as design teams utilize early silicon to diagnose problems prior to production. But this approach also is spurring questions about whether this approach is viable at 7nm and 5nm, due to the rising cost of prototyping advanced technology, such as mask tooling and wafer costs. Semiconductor designers have long b... » read more

DAC 2019 Was About More Than Just Chips
By Jo Windel - 27 Jun, 2019 - Comments: 0

Behind all the noise of the vast array of slot machines, gambling tables and bars and the bright lights of the Las Vegas strip was the large gathering of the annual Design Automation Conference, which was back in the bustling city for the first time in just under 20 years. Following its success in San Francisco last year, and indeed where it will return next July (co-located with the SEMICON... » read more

Debugging Complex SoCs
By Brian Bailey - 27 Jun, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss the debugging of complex SoCs with Randy Fish, vice president of strategic accounts and partnerships for UltraSoC; Larry Melling, product management director for Cadence; Mark Olen, senior product marketing manager for Mentor, a Siemens Business; and Dominik Strasser, vice president of engineering for OneSpin Solutions. What follows are excerpts of ... » read more

Week In Review: Design, Low Power
By Jesse Allen - 14 Jun, 2019 - Comments: 0

M&A Intel will acquire Barefoot Networks, a maker of programmable Ethernet switch silicon and the P4 networking programming language for data centers. Founded in 2013, the Santa Clara-based company has raised $155.4 million in funding. Terms of the deal were not disclosed, but Intel expects the acquisition to be final in the third quarter of this year. Tools & IP Mentor extended it... » read more

Week In Review: Design, Low Power
By Jesse Allen - 07 Jun, 2019 - Comments: 0

M&A Infineon Technologies will acquire Cypress Semiconductor for $23.85 per share in cash, or $10.1 billion. The deal will place Infineon as the number eight chip manufacturer in the world based on 2018 revenues and create an automotive powerhouse, making the combined company the largest supplier of chips to the automotive market. Infineon sees potential to reach into new industrial and co... » read more

Cyber Attacks Against Vehicles On The Rise
By Aileen Ryan - 03 Jun, 2019 - Comments: 0

Who is worried about automotive security and safety? I, for one, most definitely am! I’ve written previously about how tackling this problem makes good business sense. But the more immersed I become in this topic, the more I feel personally concerned about the implications of this, and the snail’s-pace at which the market is responding to it. I’ve just read an Upstream Security repo... » read more

Blog Review: May 22
By Jesse Allen - 22 May, 2019 - Comments: 0

Synopsys' Taylor Armerding warns that critical infrastructure is still vulnerable to cyber threats, with Kaspersky finding that 42.7% of the industrial control system computers it protected last year were attacked by malware, email phishing, or other threats. Cadence's Paul McLellan listens in as Jon Masters of Red Hat considers how to tackle speculative execution and branch prediction vulne... » read more

In-Chip Monitoring Becoming Essential Below 10nm
By Ann Mutschler - 20 May, 2019 - Comments: 0

Rising systemic complexity and more potential interactions in heterogeneous designs is making it much more difficult to ensure a chip, or even a block within a chip, will functioning properly without actually monitoring that behavior in real-time. Continuous and sporadic monitoring have been creeping into designs for the past couple of decades. But it hasn’t always been clear how effective... » read more

Blog Review: May 15
By Jesse Allen - 15 May, 2019 - Comments: 0

Cadence's Sean Dart shares an example of the kind of optimizations HLS tools can perform that would be difficult to find and implement by hand-coding RTL. Synopsys' Taylor Armerding takes a look at three cybersecurity initiatives from the U.S. government, from an IoT bill to improved voting machines, and whether they're likely to work. In a video, Mentor's Colin Walls points to why flashi... » read more

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