Why Simulation Speed Is Holding Chiplets Back

Chiplets are mainstream. The semiconductor industry has moved past the question of whether to adopt them and is now focused on scaling. IDTechEx confirms the technology is playing a crucial role across data centers, AI infrastructure, telecom, and automotive, helping overcome scaling limits, improving yields, and lowering costs. For design teams transitioning to the modular architecture, there is a misconception that the toolchain is the obstacle. However, the real constraint is simulation speed.

The State of Chiplet Adoption
With the complexity and cost involved, chiplets are not suitable for every use case; however, in high-performance computing and edge workloads, they have proven their value. The technology is now deployed in AI infrastructure, aerospace and defense applications, and autonomous vehicles, where the performance gains justify the investment. Within these domains, adoption continues to scale. However, that creates new demands, and not all of them are about the silicon. Toolchains have kept pace with hardware developments and can analyze electrical, thermal, mechanical, and optical behavior across a heterogeneous stack. The issue is not capability; it is speed.

With monolithic chips, a simulation might cover one die, process node, and set of physical interactions. In a chiplet design, the same simulation must span multiple dies, potentially from different foundries, stacked vertically or connected through interposers, each with its own properties, thermal characteristics, and failure modes. As a result, the computational demand grows substantially with each additional layer.

Research into multi-fidelity thermal modeling found that FEM simulations of 2.5D and 3D chiplet systems can take days to complete and are directly affected by geometric detail, complexity, and setup parameters. That timeline is incompatible with the pace of modern design as it forces unnecessary iteration cycles that slow time-to-insight.

Why Multi-Physics Co-Design is Non-Negotiable
Chiplet designs are inherently multi-physics problems. Heat rises between vertically stacked dies. Mechanical stress from drops or vibration affects solder connections and electrical performance. In data center applications, co-packaged optics introduce optical physics into a stack that already manages electrical and thermal interactions. None of these can be modeled in isolation. A material selected for electrical reasons may complicate heat management. Optimizing thermal performance may impact mechanical stability. The entire system has to be analyzed.

Consider what happens when a smartphone overheats while trying to connect to a weak signal. The excess heat drains the battery faster, forcing the radio to work harder, which generates more heat. In a chiplet stack, this feedback loop occurs across multiple dies, materials, and physical domains simultaneously.

Verification compounds the challenge. Traditional block-level approaches were designed for single-die systems and do not account for the interactions across multiple dies, process nodes, and packaging layers. Effective validation requires a system-level perspective from the outset, testing each die individually before confirming that performance holds once the full stack is assembled. For example, thermal and crosstalk are invisible at the component level and only appear when the entire system is modeled. Hardware-assisted environments can catch timing and interoperability issues that static analysis misses, but only when simulation keeps pace with the design.

Speeding Simulation
The answer lies in getting simulation answers faster, not in building new tools. The first lever is compute. Distributing a complex simulation across hundreds of machines, or running it on GPUs rather than CPUs, can dramatically reduce turnaround time. For many problems, this is sufficient.

Where raw compute is still not fast enough, AI-powered models offer a fundamental shift. This involves running simulations across a wide range of design parameters to train the model. Once complete, the model returns answers in seconds rather than days, reducing prototype spins and helping design teams make decisions faster. Research found that thermal models derived this way can maintain less than 1.7 degrees Celsius error at a fraction of the original compute cost.

What makes this practical is how the underlying infrastructure is accessed. Traditional EDA tools were built for human operators, running analyses through graphical interfaces, one configuration at a time. Generating the volume of data needed to train an AI model requires machines to drive the process. When the environment is accessible through scripts and APIs, varying parameters across thousands of design configurations becomes straightforward, changing the economics of simulation and removing the knowledge silos that slow cross-domain design teams.

Chiplets and Simulation
As chiplets extend beyond high-end digital into analog, mixed-signal, RF, and aerospace and defense applications, each new application brings its own physics and simulation demands. An RF chiplet operating at millimeter-wave frequencies introduces electromagnetic behavior that interacts with thermal and mechanical effects in ways that fundamentally differ from digital logic. A chiplet designed for a drone operating in extreme temperatures, with tight power budgets and strict reliability requirements, cannot be verified under the same assumptions as a data center component. Each expansion into a new domain adds a distinct set of simulation requirements. As adoption scales, the simulation challenge will only grow in complexity. Getting infrastructure right now is not just a technical decision. It is a competitive one.