Predictions: Methodologies And Tools

Cloud-based verification and software development, bigger IP blocks, machine learning, and security issues top the list for 2018.

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Predictions are divided into four posts this year. Part one covered markets and drivers. The second part looked at manufacturing, devices and companies and this part will cover methodologies and tools. In addition, the outlook from EDA executives will be provided in a separate post.

Intellectual property
As designs get larger, it should be no surprise that the size of the IP blocks would increase, as well. “The leading indicators signal a shift from designers utilizing individual IP blocks, PHY, controller, software, to the requirement of solving the complete end-to-end protocol interface challenge,” says Mick Posner, director of product marketing for USB & DisplayPort IP solutions at Synopsys. “SoC designers no longer have the time or in-house protocol expertise to integrate various IP blocks into the SoC design. Instead designers are starting to rely on the IP vendors to solve a greater part of their interface challenge.”

Posner sees individual IP blocks are being replaced by IP subsystem solutions, which have been customized to the SoC’s specific requirements. “Designers expect comprehensive RTL deliverables, specific verification, complete floor-planned GDS specific to their final chip design, and reference driver software where applicable. This, in turn, drives the need to include signal/power integrity analysis covering chip, PCB, and out to the physical connector, ensuring the greatest of margin. Subsystem-level deliverables help accelerate the design cycle, and they free up internal engineering resources to focus on their design’s functional differentiation.”

As IP gets used within more industries, new requirements emerge. “The longevity of products within system design houses will now require them to keep track of the designs/IPs for a longer time,” says Ranjit Adhikary, vice president of marketing at ClioSoft. “This will impose new challenges for existing IP management systems which will now have to track the usage of the IPs and their variations over an extended period of time. IP management systems will also have to develop new technologies to safeguard against IP theft.”

That longevity has implications for other aspects of the flow, as well. “The need for extended longevity of the devices in the IoT and automotive industry will require additional levels of testing, and result in modifications to the existing design flows-especially in the area of verification,” adds Adhikary. “In addition, the need to have easily reconfigurable SoCs also will grow and further impact traditional flows, as a number of SoCs will have embeddable FPGA in them.”

The rise of open source IP, such as RISC-V, was discussed in part two. This could increase the acceptance of open source and community sourced IP markets. “The open innovation IC story will come into full bloom in 2018,” predicts Mike Wishart, CEO of efabless.com. “Look to see multiple community-generated reference designs that can be forked to cover a multitude of interesting applications. Multiple foundries will be ‘on-boarded,’ expanding geographic and technology coverage.”

Security
There is no hiding from security issues these days. “Chip design will move from a focus on verification of functionality, to verification for security,” says Andrew Dauman, vice president of engineering at Tortuga Logic. “This is a paradigm shift that will create new de-facto standards and methodologies.”

This will impact verification initially. “We will have to provide significantly smarter verification to create secure systems,” says Frank Schirrmeister, senior group director for product management at Cadence. “The industry will need to rally to combine software-based and hardware-based offerings to allow design teams to build secure systems. Verification of safety aspects has become a key issue, not only in automotive, but more generally in aero and defense applications. Verification and even certification of compliance to safety standards will become even more important in 2018.”

Verification

Formal verification, emulation and Portable Stimulus continue to be the three areas that we can expect to see most development. “In 2018, the emulation user base will grow by targeting users outside the typical applications for hardware emulation,” says Jean-Marie Brunet, senior director of marketing for the emulation division at Mentor, a Siemens Business. “The emulation footprint will continue to grow in industry segments beyond CPU/GPU, networking, multimedia and storage. The opportunities in the automotive segment, boosted by progress on the autonomous driving car roadmap, will grow exponentially.”

“In 2018, we should continue to see formal verification as an integral part of the block-level verification strategy for networking design companies,” says Rob van Blommestein, vice president of marketing for Oski Technology. “It is practically impossible to simulate or emulate corner-case behavior for switches that support terabits of traffic, as evidenced by Barefoot Networks and Cavium. Formal is also moving up the value chain beyond block-level verification to the system-level as evidenced by its use at companies such as ArterisIP, NVIDIA and Qualcomm. Moving the use of formal earlier in the design stage will allow design architectures to be verified much sooner and therefore reduce the verification time downstream.”

Formal has long had a reputation for being difficult to use. “We will see a rise in formal program leadership and formal planning within large system houses,” continues van Blommestein. “Formal is much more exhaustive than simulation, but it does require a paradigm shift to employ, as well. Companies are recognizing that investment in this type of role and upfront planning will yield significant results.”

Schirrmeister also sees a convergence between design and verification. “The design chain has been steadily shifting its resources away from in-house/proprietary architectures, and instead adopting common processor architectures. As a result, verification flows are being optimized for processor architectures and the application domains they dominate. Closer interaction between the design chain participants – IP, semiconductor, system and OEM – will be crucial for success of highly connected systems. As a result, we will see a need for a new class of tools to enable multi-abstraction, multi-domain execution, and bring together the core competencies of the different design chain participants.”

Portable Stimulus
All eyes continue to look toward Portable Stimulus. “Portable Stimulus will take a big step forward in 2018 with the expected ratification of the Accellera Portable Stimulus Standard (PSS) v1.0, and the release of vendor tools supporting it,” says Steve Brown, product management director for Cadence’s System & Verification Group. “This will give existing and sidelined users confidence to invest in creating the models and deploying their projects. We will see a blossoming ecosystem to add value and assist with learning and adoption of PSS. Attention will shift to the topics of coverage and reuse, with the relationship between PSS and UVM addressed in methodology.”

It helps to understand why this will be so important to the industry. “Twenty years ago, the semiconductor design industry had the luxury of attracting some of the greatest minds in the high-tech world,” explains Adnan Hamid, chief executive officer of Breker Verification Systems. “Thankfully, most of those are still in the industry and have become the resident gurus in the top design houses of the world. But today, the Internet, machine learning and a number of other areas are more attractive to top-tier college graduates. This means we have to find ways to encapsulate the knowledge and experience of the older members of the industry and transfer that into tools and methodologies that make younger engineers more productive. Portable Stimulus is a great example of this in that it enables design intent to be captured in a form that is similar to the process used by experienced verification architects. From this model of intent, testbenches can be automatically synthesized, achieving greater efficiency than the existing methodology, especially for SoC-types of designs.”

PSS will impact all aspects of verification. “In 2018, the portable stimulus initiative will include emulation,” says Lauro Rizzatti, an independent verification expert. “Further, emulation will become mainstream and mandatory for design verification of chips serving the automotive industry. Checking for security in automotive chip designs will require trillions, if not quadrillions, of cycles (peta-cycles). Finally, emulation datacenters will get more and more attention.”

Aspects of PSS remain contentious within the industry. “At Verific Design Automation, we always keep a keen eye out on new standards in the electronic design, test, and verification space,” says Michiel Ligthart, President and COO at Verific. “We do not necessarily drive them, but we definitely monitor where they are going. Portable Stimulus seems like a good idea with some questionable choices such as a domain specific language (DSL) being defined right beside a competing C++ syntax. We already had a first commercial inquiry about if and when we will support a parser for it. But for that to happen, it has to move out of Accellera and into the IEEE domain, which I am sure eventually will happen.”

Machine learning
The EDA industry is still trying to find the best ways to apply this technology. “In 2017, the technology world became enamored with machine learning (ML) and artificial intelligence (AI),” says Larry Melling, product management director for Cadence’s System & Verification Group. “The first EDA tools leveraging these technologies came to market in 2017. 2018 will see ML applied in both the EDA and semiconductors industries. It will impact IP sub-systems that include neural networks and deep learning in SoCs. ML will continue to grow in design and implementation applications, and begin impacting smarter verification solutions and the productivity throughput results users can achieve.”

It also may bring new classes of tools into existence. “Building reliable and accountable machine learning models will have a direct impact on design practices and development tools because machine learning is essentially a statistical method,” says Raik Brinkmann, president and CEO of OneSpin Solutions. “This is very different from the traditional engineering practices. New types of bugs, such as data-driven ones, need to be addressed.”

As data rather than people define the specification, validation of data with regard to its ability to cover all relevant application scenarios becomes a new challenge, Brinkman says. “A combination of traditional methods, such as requirement engineering or formal analysis with statistical, data-driven approaches will be required. As a result, new tools will be needed to support these processes.”

The cloud

Having design and EDA move into the cloud has been predicted for almost as long as ESL. “Design in the cloud doesn’t seem to be as unthinkable a concept as it once was,” observes Bob Smith, executive director for the ESD Alliance. “In 2018, expect to see momentum shift as more semiconductor companies evaluate cloud services for future design projects because the benefits are unmistakable. Engineering managers, who don’t have hardware resources available to manage their groups’ increasingly complex designs, find they can reduce capital expenditures by moving to the cloud. Perhaps most telling, security concerns have been addressed, alleviating what many industry watchers considered to be the most difficult adoption barrier to overcome. While I don’t expect a wholesale move to the cloud in 2018, we will begin to see more examples of design in the cloud.”

Jim Hogan, managing partner at Vista Ventures, shares a similar view. “Adoption of the cloud in hardware design will grow as a means to address intense compute power demands during peak periods. The advantages of elastic compute power, reduced cost of ownership, and access to perpetually modern hardware will then foster increased cloud utilization, in general.”

Shiv Sikand, vice president of engineering for IC Manage, also weighs in. “System and semiconductor companies will more actively use cloud services, initially driven by the need for elastic compute power during peak loads. Running remote sites as cloud instances will also be utilized for increased cost reduction.”

Could this be the year that software development makes a breakthrough in the cloud? “It remains one of the last sectors working offline but the clear benefits of SaaS and enhanced security through dockerized provisioning could see a step-change for software professionals,” says Maximilian Odendahl, CEO of Silexica. “I predict we will see some big announcements and acquisitions by cloud providers as software development accepts now is the time to move.”

And speaking of software, “toward the last half of 2017 I really saw growing uncertainty and fear about the humongous shift from (static) C to (dynamic) C++ code,” observes Odendahl. “No one is clear on how to tackle that challenge. The only conclusion is that it is becoming harder and harder to achieve a proper system design manually. This year we will see more companies changing to automated processes to migrate their software onto heterogeneous multicore platforms.”

Related Stories
Predictions: Manufacturing, Devices And Companies
New architectures, materials and equipment could have a huge impact on the chip industry.
Predictions: Markets And Drivers
Part 1: What advancements can we expect to see in 2018, which markets will drive the industry, and what are the major challenges that have to be addressed?
Follow The Moving Money
How economic considerations are affecting designs at advanced nodes and across geographies.



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