ALD Market Heats Up

Amid the shift to 3D NAND, finFETs and other device architectures, the atomic layer deposition (ALD) market is heating up on several fronts.

Applied Materials, for example, recently moved to shakeup the landscape by rolling out a new, high-throughput ALD tool. Generally, ALD is a process that deposits materials layer-by-layer at the atomic level, enabling thin and conformal films on devices.

Meanwhile, ASM International, Lam Research, Tokyo Electron (TEL), Ultratech and others are also stepping up their efforts in ALD, and for good reason: the applications are rapidly expanding for ALD.

Traditionally, ALD has been used for DRAM capacitor and high-k applications. Now, toolmakers are chasing after some relatively new and sizable ALD markets, namely 3D NAND and multi-patterning for advanced logic. Other emerging ALD markets include fin doping, interconnects, ReRAMs and selective deposition.

“ALD has become more important for chip production,” said Han Jin Lim, an ALD expert and a technical member at Samsung Semiconductor’s R&D Center. “As the structure of a chip becomes more complicated, thinner and more conformal films are required. The quality of the films (must also be) maintained. ALD is the best methodology to achieve them.”

Even though ALD enables thin and conformal films, the process is sometimes slow and expensive. And not all ALD tools are alike. Vendors offer different types of ALD machines in what has become a complex and fragmented market.

“Atomic level processes have been employed for a while, but since they are generally expensive, they are only used when needed,” said Andreas Knorr, deputy director of technology research at GlobalFoundries. “But we now see an increased use of atomic layer processing as a result of continued scaling. The added control and precision of atomic level processing can enable next-generation devices and architectures. Perfectly conformal films with exact engineered composition and atomic bonding, as well as the controlled removal of materials, will be required in most sections for the manufacturing flow.”

What is ALD?
ALD has been around since the 1970s. But it entered the limelight at 45nm, when Intel used ALD to deposit a high-k material called hafnium for the gate stack in a transistor. Ultimately, high-k replaced silicon dioxide, which was then running out of steam. This, in turn, enabled chipmakers to scale their devices, thereby keeping the industry on .

Basically, there are two types of ALD—thermal and plasma enhanced. Thermal ALD involves a binary process with two reactants—A and B. The first reactant, A, is pumped into the ALD chamber. The wafer is processed and then the chemistries are purged. Then, the second reactant, B, undergoes the same step.

In plasma-enhanced ALD, the reactions are plasma-based. “The plasma-enhanced method for ALD is being driven by low-temperature applications,” said Bob Hollands, director of technical marketing at ASMI.

In total, the ALD tool market for semiconductor applications is projected to reach $1.2 billion over the next three to four years, up from $600 million in 2014, according to ASMI.

But near term, the ALD market looks soft amid a downturn in the memory business. The ALD tool business is expected to grow by a mere 1% in 2015 and 0.25% in 2016, according to Dean Freeman, an analyst with Gartner.

In 2014, ASMI was the leader in the ALD tool market with a 53% share, followed in order by TEL (27%), Jusung (6%), Lam Research (5%), Wonik IPS (5%) and Aixtron (2%), Freeman said.

Applied Materials, the new kid on the ALD block, hopes to make a dent in a competitive and fragmented market. “In tungsten, Applied is going up against the incumbent in Lam,” Freeman said. “And in plasma, they are going up against ASMI, Lam and TEL.”

Still, Applied Materials insists there is room for a new competitor. “You are getting to the point where conventional ALD is just simply running out of steam,” said David Chu, strategic marketing director at Applied Materials. “We have things like patterning, capacitor dielectrics or 3D NAND. Those things are still on the order of about 100 angstroms or 200 angstroms. Using conventional ALD to grow 200 angstrom films ends up being a challenge.”

Applied Materials is selling a spatial-based ALD tool, which is one of several configurations for ALD. The others include furnace/batch and single-wafer tools. Furnace/batch systems handle a multitude of wafers and enable thicker films. Used by DRAM makers, batch systems are relatively fast, but there is a trade-off in terms of uniformities.

Single-wafer ALD tools are used in applications, where the uniformity specs are thinner and tighter. Single-wafer, which is used to deposit high-k dielectrics in logic, are also time-based systems. In time-based tools, the reactions take place in a chamber for a set or given time.

In contrast, spatial ALD tools are mini-batch systems. A number of wafers are placed in the system. The wafers travel to various zones. At each zone, a reactant is pumped into the chamber. The wafer is processed and is then moved to the next zone.

In the case of Applied’s new spatial tool, the system can solve a major problem–throughput. Applied’s system eliminates the purging process, thereby boosting ALD productivity by fourfold, Applied’s Chu said.

Generally, there is no superior tool type. Batch, single-wafer and spatial tools are geared for specific applications. And each tool type has its advantages and disadvantages. “Throughput is still one of the challenges,” Samsung’s Lim said. “This could be overcome by multi-wafer or spatial-type ALD tools. Another challenge is the proper precursor development for ALD to acquire the required film criteria.”

And still to be seen, however, is what impact will ALD have on devices at advanced nodes. “As it pertains to atomic level processes, we don’t see any immediate impact,” GlobalFoundries’ Knorr said. “(There is a) reduced number of atoms involved, but while finite, it’s still pretty large. Of course, dimensional scaling leads us into the regime where quantum effects and statistical fluctuations need to be comprehended. But these are more a result of scaling than the process.”

The ALD apps
For years, meanwhile, ALD has been used in two main areas—high-k and DRAM. The deposition of high-k materials for logic is still an important application for ALD, but this only represents a small part of the overall ALD market. As it turns out, ALD is responsible for depositing only one or so layers of high-k materials for the gate stack.

In DRAM, the challenge is to scale the capacitor. The DRAM capacitor resembles a vertical, cylindrical-like structure. At each node, the capacitor is becoming smaller, but the charge must remain constant within the structure.

For the capacitor, DRAM makers employ a metal-insulator-metal (MIM) stack using high-k dielectrics. For future DRAMs at the 1nmx node, the capacitor may require ultra high-k materials. In both cases, ALD is used to deposit high-k materials.

Meanwhile, the next big applications for ALD are 3D NAND and multi-patterning for logic. 3D NAND is the successor to today’s planar NAND. 3D NAND resembles a skyscraper, in which horizontal levels are stacked and then connected using tiny vertical channels.

Making 3D NAND is easier said than done. The 3D NAND flow starts with a substrate. Then, vendors face the first challenge in the flow—alternating stack deposition. Using chemical vapor deposition (CVD), alternating stack deposition involves a process of depositing and stacking thin films layer by layer on the substrate.

Then, high-aspect ratio trenches are etched from the top of the device to the substrate. After the trenches are formed, the device requires contacts. For this, the device is backfilled with a conductor using a metal deposition step. Using ALD, metal deposition is one of the harder steps in the flow. The idea is to fill the tiny caves and holes in the structure with materials using a non-line-of-sight tool.

In many cases, tungsten is used for metal deposition in 3D NAND. “The tungsten lines are the wordlines in the 3D NAND device,” said Rick Gottscho, executive vice president of global products at LAM Research, in a recent presentation. “The critical thing is to make sure there are no voids. It’s not easy. You must get (the materials) into the middle. Otherwise, you could have an open line and then you have yield loss.”

The latest 3D NAND chips have 48 layers. As 3D NAND scales beyond 48 layers, the specs will become tighter and more precise. Clearly, ALD, along with CVD and etch, must step up to meet the challenge.

Another big market for ALD is multi-patterning, particularly in self-aligned double patterning (SADP) and self-aligned quadruple pattering (SAQP). SADP/SAQP, which have been used in DRAM and NAND, are now moving into logic.

At 10nm, for example, some foundries are moving to SAQP. This process uses one lithography step, and additional deposition and etch steps, to define a spacer-like feature. In this process, plasma enhanced ALD is used to create precise spacer layers. The spacer layers eventually become the critical sidewalls of the pattern.

“The key challenges (for multi-patterning) are variability and cost. There are two sources of variability when you do spacer deposition. One, there is a potential for variation in the thickness of this film, center to edge across the wafer,” Lam’s Gottscho said. “You can also cause erosion of the mandrel. Any erosion of that mandrel is going to affect the final critical dimension.”

Cost is another issue. “The cost problem comes about for the simple fact that you have more processes going on. That adds cost and complexity,” he added.

Meanwhile, there are other emerging applications for ALD. Fin doping is one example. In addition, the industry is rushing to develop a new technology called selective deposition. Combining novel chemistries with ALD, selective deposition involves a process of depositing materials and films in exact places.

“Selective deposition is still in the R&D stage, but it’s approaching reality,” ASMI’s Hollands said. “The selective method is powerful, but it’s very challenging.”