Clock tree synthesis; UCIe 3.0; system-centric approach to 3D-IC; finding unintended consequences; AI-defined engineering; FMCW radar.
Cadence’s Pamula Sai Srinivas explains why clock tree synthesis is essential to ensuring that the clock signal is distributed in a way that helps achieve timing closure and maintain synchronization, performance, and reliability.
Synopsys’ Sajani Patel, Varun Agrawal, and Manuel Mota check out what’s new in UCIe 3.0, including doubling the maximum data rate to 64 GT/s, runtime recalibration, and extended sideband reach.
Siemens’ John McMillan notes that success in 3D-IC requires thinking beyond individual components with a system-centric design approach and suggests early prioritization of multi-physics verification and design for manufacturing/yield/test.
Arm’s Annie Tallund explains Yellow Teaming, a methodology intended to surface the unintended consequences of product design before you ship, and how it can provide guidance for responsible AI development as well as drive better product design.
Keysight’s Roberto Piacentini Filho suggests an AI-defined engineering workflow that can take plain language commands and automatically configure models, set constraints, run sweeps, analyze results, and flag problem scenarios.
Ansys’ Aaron Talwar shows how phase noise modeling enables more precise testing under real-world conditions of frequency modulated continuous wave (FMCW) radar systems used for ADAS and AV.
SEMI’s Paul Trio provides an update on data standardization efforts, including guidance on how to identify manufacturing equipment data provided by the equipment supplier that can be used in equipment engineering or analysis applications.
And don’t miss the blogs featured in the latest Manufacturing, Packaging & Materials newsletter:
Lam Research’s Brett Lowe examines the stresses on SiN and oxide layers as 3D NAND memory approaches 300 layers.
Synopsys’ Anders Blom shows how to assess the intrinsic physical behavior of new materials before they are even synthesized.
Microtronic’s Errol Akomer explains how to catch partially defective die before they make it into a product.
SEMI’s Sungho Yoon finds a discrepancy between flat wafer shipments and booming fab investments and AI chip demand.
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