Hybrid Architecture Blends Best Of Both Worlds


Quadric chose the brand name Chimera to describe the company’s novel general purpose neural processing unit (GPNPU) architecture. According to the online Oxford dictionary, in biology a chimera is “an organism containing a mixture of genetically different tissues (or DNA).” Quadric made that naming choice to reflect the fact that its Chimera GPNPU has characteristics of both conventiona... » read more

BOLT Optimization Technology Could Bring Obvious Performance Uplift On Arm Server


BOLT is a post-link optimization technology which builds on LLVM framework, which leverages perf tool to collection sampling data and convert the executable into an optimized version. After evaluating BOLT on several workloads such as MySQL, Redis, memcached and nginx on Arm server, we could see obvious performance uplift. This blog post illustrates the methods used to enable BOLT and per... » read more

Unlocking PPA Benefits of Backside Routing


The power delivery network (PDN) is a critical part of any modern semiconductor device. Even with advanced power-saving technologies, today’s chips are hungry for power. Traditionally, power is distributed through metal layers on the same side of the substrate as the signal metal layers. This creates competition for the available layers and pushes the limits of fabrication technology to add m... » read more

Performance Boost In Powerful Real-Time Cortex-R Processor Using Data Prefetch Control


High-performance processors employ hardware data prefetching to reduce the negative performance impact of large main memory latencies. An effective prefetching mechanism can improve cache hit rate significantly. Data prefetching boosts the execution performance by fetching data before it is needed. While prefetching improves performance substantially on many programs, it can significantly red... » read more

Hybrid Methodology To Extract Kinetic And Magnetic Inductances For Superconductor Technologies


Integrated circuits (ICs) using superconductors have emerged as the technology of choice for artificial intelligence (AI), data centers, and cloud computing. However, innovative technology requires equally innovative physical verification solutions to ensure that these superconductor ICs deliver the performance and reliability they promise. We introduce an innovative hybrid methodology to extra... » read more

Low-Power Relaxation Oscillator With Temperature-Compensated Thyristor Decision Elements


This paper presents a low-power 140 kHz relaxation oscillator (ROSC) for low-frequency clock generators and timers. In voltage-mode ROSCs, unavoidable shunt current consumption results from voltage slewing at the integration capacitor. The proposed circuit employs CMOS thyristor-based decision elements which effectively reduce shunt currents by exploiting internal positive feedback. A complemen... » read more

PCI Express Test Overview


PCl Express, short for Peripheral Component Interconnect Express, is a high-performance and high-bandwidth serial communication interconnect standard. First proposed by Intel and further developed by the Peripheral Component Interconnect Special Interest Group (PCI-SIG) in replacement of bus-based communication architecture, such as PCI, PCI Extended (PCI-X), and Accelerated Graphics Port (AGP)... » read more

Quantum Well Design Basics


Key Takeaways The choice of materials for the quantum well and barrier layers is paramount. Materials must have compatible lattice structures to minimize defects, with common combinations including GaAs/AlGaAs, InGaAs/InP, and GaN/AlGaN. The width of the quantum well significantly influences the energy levels and density of states, where narrower wells result in greater separation betwe... » read more

Amplify Simulation Via Effective Data And Process Management


Over the past 50 years, engineering simulation has proven its value by reducing development time and costs, as well as dramatically improving product performance. By subjecting their designs to real-world physical forces in a risk-free virtual environment, product development teams can identify issues and address them at an early stage, thus minimizing expensive rework, prototyping, and physica... » read more

Research Bits: April 8


Annealing processor Researchers from the Tokyo University of Science designed a scalable, fully-coupled annealing processor with 4096 spins on a single board with 36 CMOS chips, with parallelized capabilities for accelerated solving of combinatorial optimization problems. "We want to achieve advanced information processing directly at the edge, rather than in the cloud, or performing prepro... » read more

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