Advances In 3D CMOS Image Sensors Optical Modeling: Combining Realistic Morphologies With FDTD


This paper describes an innovative methodology to investigate the relationship between device morphology and the optical performance of CMOS image sensors. By coupling a FDTD-based 3D Maxwell solver with silicon-accurate process modeling software, we have been able to analyze the sensitivity of image sensor quantum efficiency with respect to statistical variations in nm-scale device topology. A... » read more

Process To Produce High Aspect Ratio Electroplated Copper Pillars On 300 mm Wafers


This work provides details of a complete and partially optimized process to manufacture high aspect ratio copper pillars with heights of up to 80 µm on 200 and 300 mm wafers. Across wafer uniformity data for all materials and process steps are given. Results will show excellent resist adhesion on copper and electroplating durability. Cross sectional SEM analysis of resist and electroplated pil... » read more

New SiC Power Modules Deliver Greater Power Densities In Smaller Packages Than Si IGBTs


With the shift toward electrical power for a wide range of applications, including power generation, energy storage, and transportation, comes the need to build higher performance electrical conversion and control systems to fuel the future of electric-powered systems. To do so, there is a greater demand for more compact, higher power density, and high temperature operating power modules. Un... » read more

Manufacturing Bits: Oct. 15


Sandia’s fab upgrade Sandia National Laboratories has completed the first phase of a three-year upgrade program in its semiconductor wafer fab. The goal of the program is to convert Sandia’s Albuquerque, N.M.-based fab from 150mm (6-inch) to 200mm (8-inch) wafer sizes. As part of the move, Sandia is converting its 0.35-micron (350nm) rad-hard process from 150mm to 200mm. The process is ... » read more

Week In Review: Manufacturing, Test


Fab tools A consortium of 31 companies have launched a new project, called the “Advanced packaging for photonics, optics and electronics for low cost manufacturing in Europe.” The program is referred to as APPLAUSE. With a budget of 34 million euros, the project is being coordinated by ICOS, a division of KLA. “APPLAUSE will focus on advanced optics, photonics and electronics packagin... » read more

Manufacturing Bits: Oct. 9


World’s strongest silver A group has developed what researchers say is the world’s strongest silver. The silver demonstrated a hardness of 3.05 GPa, which is 42% stronger than the previous world record. The University of Vermont, Lawrence Livermore National Lab, the Ames Laboratory, Los Alamos National Laboratory and UCLA contributed to the work. Silver is an element with high electr... » read more

Week In Review: Manufacturing, Test


Packaging and test In a major deal that has some implications in the OSAT supply chain, South Korea’s Nepes has taken over Deca Technologies’ wafer-level packaging manufacturing line in the Philippines. In addition, Nepes has also licensed Deca’s M-Series wafer-level packaging technology. This includes fan-in technology as well as wafer- and panel-level fan-out. It also includes an ad... » read more

Manufacturing Bits: Oct. 1


3D balloon printing Using an elastomeric or stretchy balloon, the University of Houston and the University of Colorado have developed a new 3D printing method as a means to develop three-dimensional curvy electronic products. The technology involves the field of 3D printing, sometimes known as additive manufacturing (AM). In 3D printing, the goal is to develop parts layer-by-layer using mat... » read more

Week In Review: Manufacturing, Test


Chipmakers United Microelectronics Corp. (UMC) has satisfied all closing conditions for the full acquisition of Mie Fujitsu Semiconductor Ltd. (MIFS), the former 300mm wafer foundry joint venture between UMC and Fujitsu Semiconductor Ltd. (FSL). The completion of the acquisition is scheduled for Oct. 1. In 2014, FSL and UMC agreed for UMC to acquire a 15.9% stake in MIFS from FSL through pr... » read more

Influence Of SiGe On Parasitic Parameters in PMOS


In this paper, simulation-based design-technology co-optimization (DTCO) is carried out using the Coventor SEMulator3D virtual fabrication platform with its integrated electrical analysis capabilities [1]. In our study, process modeling is used to predict the sensitivity of FinFET device performance to changes in a silicon germanium epitaxial process. The simulated process is a gate-last flow p... » read more

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