Which Foundry Is In The Lead? It Depends.


The multi-billion-dollar race for foundry leadership is becoming more convoluted and complex, making it difficult to determine which company is in the lead at any time because there are so many factors that need to be weighed. This largely is a reflection of changes in the customer base at the leading edge and the push toward domain-specific designs. In the past, companies like Apple, Google... » read more

Week In Review: Semiconductor Manufacturing, Test


Fallout from the new U.S. export controls continues. Under new regulations, companies looking to supply Chinese chipmakers with advanced manufacturing equipment (<14nm) must first obtain a license from the U.S. Department of Commerce. In addition, U.S. persons (citizens and permanent residents) are barred from supporting China’s advanced chip development or production without a license. ... » read more

SiPs: The Best Things in Small Packages


System-in-package (SiP) is quickly emerging as the package option of choice for a growing number of applications and markets, setting off a frenzy of activity around new materials, methodologies, and processes. SiP is an essential packaging platform that integrates multiple functionalities onto a single substrate, which enables lower system cost, design flexibility, and superior electrical p... » read more

Wafer Cleaning Becomes Key Challenge In Manufacturing 3D Structures


Wafer cleaning, once a rather mundane task as simple as dipping wafers in cleaning fluid, is emerging as one of the top major engineering challenges for manufacturing GAA FETs and 3D-ICs. With these new 3D structures — some on the horizon but some already in high-volume manufacturing — semiconductor wafer equipment and materials suppliers in the wet cleaning business are at the epicenter... » read more

What’s Different About Next-Gen Transistors


After nearly a decade and five major nodes, along with a slew of half-nodes, the semiconductor manufacturing industry will begin transitioning from finFETs to gate-all-around stacked nanosheet transistor architectures at the 3nm technology node. Relative to finFETs, nanosheet transistors deliver more drive current by increasing channel widths in the same circuit footprint. The gate-all-aroun... » read more

Additive Techniques For Flexible Hybrid Electronics Packaging And Integration With Human Body


By Gity Samadi and Paul Semenza Flexible hybrid electronics (FHE) has spawned the development of novel packaging techniques to overcome the application limitations of the rigid boards, high-temperature solders, bulky component packages, and insertion processes used in traditional printed circuit boards. Thin, flexible substrates, bare die, and combinations of printed and small-format package... » read more

Insights Into Advanced DRAM Capacitor Patterning: Process Window Evaluation Using Virtual Fabrication


With continuous device scaling, process windows have become narrower and narrower due to smaller feature sizes and greater process step variability [1]. A key task during the R&D stage of semiconductor development is to choose a good integration scheme with a relatively large process window. When wafer test data is limited, evaluating the process window for different integration schemes can... » read more

Production Testing Of Discrete Power Products


By Vineet Pancholi and Dennis Dinawanao Metal Oxide Silicon Field Effect Transistors (MOSFETs), Insulated Gate Bipolar Transistors (IGBTs), Bipolar Junction Transistors (BJTs), diodes, and application specific multi-transistor packaged modules are some of the more popular discrete products. Switches control the flow of current within a circuit. MOSFETs are a building block of most electronic... » read more

Realization Of Sub-30-Pitch EUV Lithography Through The Application Of Functional Spin-On Glass


Photoresist metrics such as resolution, roughness, CD uniformity, and overall process window are often aimed to realize the full potential of EUV lithography. From the view of the materials supplier, improvements over the aforementioned metrics can be achieved by optimizing the functional materials used under the resist. The underlayers can significantly enhance the resist performance by provid... » read more

Metal Oxide Resist (MOR) EUV Lithography Processes For DRAM Application


This paper reports the readiness of key EUV resist process technologies using Metal Oxide Resist (MOR) aiming for the DRAM application. For MOR, metal contamination reduction and CD uniformity (CDU) are the key performance requirements expected concerning post exposure bake (PEB). Based on years of experience with spin-on type Inpria MOR, we have designed a new PEB oven to achieve contamination... » read more

← Older posts Newer posts →