category: Test, Measurement and Analytics

category: Auto, Security & Edge AI

Extracting Intrinsic Mechanical Properties Of Thin Low-Dielectric Constant Materials With iTF Analysis
By Bruker - 12 Apr, 2022 - Comments: 0

This white paper focuses on the optimization and use of Bruker’s iTF software package for the extraction of intrinsic (substrate independent) mechanical properties, particularly for thin, low-k materials. These considerations are split into two main parts: Measurement procedure (Section II) and iTF execution (Section III). The former outlines important aspects of acquiring proper experimental... » read more

Made in the Cloud!
By Synopsys - 12 Apr, 2022 - Comments: 0

While software developers have been building and delivering software in the cloud for many years now, how much IC hardware is “made in the cloud”? We’re here to help you understand the case for IC hardware development in the cloud and answer the most common questions. Download the paper and learn: Why isn’t everybody doing it? Why cloud? Why now? Can you afford to ignore i... » read more

Silicon Lifecycle Management’s Growing Impact On IC Reliability
By Ed Sperling - 12 Apr, 2022 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to talk about silicon lifecycle management, how it's expanding and changing, and where the problems are, with Prashant Goteti, principal engineer at Intel; Rob Aitken, R&D fellow at Arm; Zoe Conroy, principal hardware engineer at Cisco; Subhasish Mitra, professor of electrical engineering and computer science at Stanford University; a... » read more

Site-To-Site Variation In Parallel Test
By Ed Seng - 16 Mar, 2022 - Comments: 0

From wafer to system level test, parallel test execution delivers significant benefits, including reduced costs, yet it’s never as simple as that PowerPoint slide you present to management. An engineering effort is required to balance the thermo-electrical challenges that occur as you increase the number of sites to be tested, or the number of slots in a burn-in oven or system level te... » read more

Fundamental Shifts In IC Manufacturing Processes
By Ed Sperling - 14 Mar, 2022 - Comments: 2

High chip value and 3D packaging are changing where and how tests are performed, tightening design-for-reliability and accelerating the shift of tools from lab to fab. Heterogeneous integration and more domain-specific designs are causing a string of disruptions for chip manufacturers, up-ending proven fab processes and methodologies, extending the time it takes to manufacture a chip, and ul... » read more

Software-Driven and System-Level Tests Drive Chip Quality
By Bryon Moyer - 08 Mar, 2022 - Comments: 0

Traditional semiconductor testing typically involves tests executed by automatic test equipment (ATE). But engineers are beginning to favor an additional late-test pass that tests systems-on-chip (SoCs) in a system context in order to catch design issues prior to end-product assembly. “System-level test (SLT) gives a high-volume environment where you can test the hardware and software toge... » read more

Addressing The ABF Substrate Shortage With In-Line Monitoring
By Wesley Chou - 08 Mar, 2022 - Comments: 1

Ajinomoto build-up film (ABF) substrate has been a key component in chip manufacturing since its introduction shortly before the turn of the millennium. Substrates made with Ajinomoto build-up film – an electrical insulator designed for complex circuits – are found in PCs, routers, base stations, and servers. Looking ahead, the ABF substrate market will continue to grow, with revenue up ... » read more

A Practical Approach To DFT For Large SoCs And AI Architectures, Part II
By Rahul Singhal - 08 Mar, 2022 - Comments: 0

By Rahul Singhal and Giri Podichetty Part I of this article discusses the design-for-test (DFT) challenges of AI designs and strategies to address them at the die level. This part focuses on the test requirements of AI chips that integrate multiple dies and memories on the same package. Why 2.5D/3D chiplet-based designs for AI SoCs? Many semiconductor companies are adopting chiplet-based d... » read more

Auto Chipmakers Dig Down To 10ppb
By Anne Meixner - 08 Mar, 2022 - Comments: 0

How do engineers deliver 10 defective parts per billion (Dppb) to auto makers if they only screen 1 million parts per year? Answer: By comprehending failure mechanisms and proactively screening for them. Modern automobiles contain nearly 1,000 ICs that must perform over the vehicle’s life (15 years). This drives quality expectations ever higher. While 10 Dppm used to be a solid benchmark, ... » read more

Enabling Silicon Lifecycle Solutions
By Aileen Ryan - 08 Mar, 2022 - Comments: 0

The concepts of product lifecycle management (PLM) should be familiar, although the semiconductor industry has yet to adopt a system for managing the entire lifecycle of a product from inception through design, realization, deployment, and field service, right through to end-of-life activities such as final disposal. Now, a combination of business and technical pressures is bringing PLM capabil... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy