category: System-Level Design

category: Auto, Security & Edge AI

RISC-V Gains Its Footing
By Ann Mutschler - 26 Feb, 2018 - Comments: 3

The RISC-V instruction-set architecture, which started as a UC Berkeley project to improve energy efficiency, is gaining steam across the industry. The RISC-V Foundation's member roster gives an indication who is behind this effort. Members include Google, Nvidia, Qualcomm, Rambus, Samsung, NXP, Micron, IBM, GlobalFoundries, UltraSoC, Siemens, among many others. One of the key markets for... » read more

The Week In Review: Design
By Jesse Allen - 23 Feb, 2018 - Comments: 0

Tools & IP Pro Design launched three new proFPGA Zynq UltraScale+ FPGA modules for SoC and IP prototyping. The modules combine FPGA logic with quad-core ARM Cortex-A53 and dual-core ARM Cortex-R5 processors and on-board interfaces. The modules offer a total of up to 5 extension sites with 531 standard I/Os and 16 multi-gigabit transceivers (MGTs). The board allows a maximum point-to-point ... » read more

Who Will Regulate Technology?
By Ed Sperling - 22 Feb, 2018 - Comments: 0

Outside regulation and technological innovation don't mix well, particularly when it comes to modern electronics, but the potential for that kind of oversight is rising. In the past, most of the problems involving regulation stemmed from a lack of understanding about technology and science. This is hardly a new phenomenon. It literally dates back centuries. Galileo was forced to recant helio... » read more

A Reliability Baseline Is Essential For Today’s Complex IC Designs
By Matthew Hogan - 22 Feb, 2018 - Comments: 0

Design rule checking (DRC) represents a common platform by which we can all compare relative rule complexity. The industry expectation is that all foundries will provide complete DRC and layout vs. schematic (LVS) rule decks at all process nodes for the successful tape-out of IC designs. However, not only are DRC operations growing significantly (Figure 1), but the scope of the rules needed to ... » read more

Regain Your Power With Machine Learning
By Shekhar Kapoor - 22 Feb, 2018 - Comments: 0

It wasn’t too long ago that machine learning (ML) seemed like a fascinating research topic. However, in no time at all, it has made a swift transition from a world far-off to common presence in news, billboards, workplaces, and homes. The concept itself is not new but evidently what has caused it to take off is the rapid growth of data in many applications and more computational power. Closer... » read more

Functional Safety: A Way Of Life
By Rajesh Ramanujam - 22 Feb, 2018 - Comments: 0

Rejuvenated over the holidays and back in full swing. This might be TMI, but I have been doing some meditative yoga and I seemed to have finally discovered myself. Though I am partly kidding, it does bring us to theme for this blog. As we tackle a new year and all the challenges it brings, I have been engaged with mindfulness and meditative yoga, which looks at a holistic approach to bring t... » read more

How SoC Interconnect Enables Flexible Architecture For ADAS And Autonomous Car Designs
By Kurt Shuler - 22 Feb, 2018 - Comments: 0

When the mobile phone era saw its fastest growth, the design teams that were the most innovative were able to introduce game-changing features before anyone else. Those companies also had the most configurable interconnect IP, allowing them to adapt to quickly changing market needs faster than their competition. Now, nearly a decade later, when autonomous driving is quickly moving into the m... » read more

Debugging Debug
By Brian Bailey - 22 Feb, 2018 - Comments: 2

There appears to be an unwritten law about the time spent in debug-it is a constant. It could be that all gains made by improvements in tools and methodologies are offset by increases in complexity, or that the debug process causes design teams to be more conservative. It could be that no matter how much time spent on debug, the only thing accomplished is to move bugs to places that are less... » read more

Inside UVM, Take Two
By Vatsal Choksi - 22 Feb, 2018 - Comments: 0

In this blog, my major focus is on explaining the concepts such as Sequence, Sequencer, Driver and showing how the communication takes place from sequence to sequencer and from sequencer to driver. In the previous blog, I included a top-level diagram of the UVM structure, showing different base classes. So, let’s look at the main concepts and follow the communication mechanism they use for... » read more

Deconstructing Deep Learning
By Mike Gianfagna - 22 Feb, 2018 - Comments: 0

I discuss AI and deep learning a lot these days. The discussion usually comes back to “what is a deep learning chip?” These devices are basically hardware implementations of neural networks. While neural nets have been around for a while, what’s new is the performance advanced semiconductor technology brings to the party. Applications that function in real time are now possible. But wh... » read more

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