category: System-Level Design

category: Auto, Security & Edge AI

Toward Continuous HW-SW Integration
By Ann Mutschler - 25 May, 2017 - Comments: 0

Hardware is only as good as the software that runs on it, and as system complexity grows that software is lagging behind. The way to close that gap is to improve the [getkc id="100" kc_name="methodology"] for developing that software in the first place. That includes making sure updates are verified and tested before being pushed out to devices, adding the same kinds of detailed checks that ... » read more

It’s Show Time
By Henry Chan - 25 May, 2017 - Comments: 0

It’s been a busy season. The weather has warmed here in the desert and as the trees and greenery enliven in spring, The whole industry is bursting with activity. From DVCon to the International Symposium on FPGAs in the United States to Embedded World and CTIC in Europe, there have been a number of important developments in verification, embedded systems, and DO-254. The DVCon U.S. Confere... » read more

Capturing The Future, Frame By Frame
By Stephen Barton - 25 May, 2017 - Comments: 0

A lot has changed over the past year, and more changes are on the way. Consider what's happening in API tracing. All of the functions from the Vulkan specification can be traced correctly in MGD. This means that you will be able to see exactly what Vulkan calls your application makes and in what order. You will also be able to see what threads each of these function calls occur in. Figu... » read more

Verification Unification
By Brian Bailey - 25 May, 2017 - Comments: 0

There is a lot of excitement about the emerging [getentity id="22028" e_name="Accellera"] [getentity id="22863" e_name="Portable Stimulus”] (PS) standard. Most of the conversation has been about its role in [getkc id="11" kc_name="simulation"] and [getkc id="30" kc_name="emulation"] contexts, and in the need to bring portability and composability into the verification flow. Those alone are st... » read more

Five Things You Need To Know Before Selecting An RTOS
By Mentor, a Siemens Business - 24 May, 2017 - Comments: 0

Almost any embedded device is likely to need an operating system of some description. Making the decision to use an OS, selecting it and planning its deployment are all challenging. In this paper, we will take a detailed look at the 5 key issues facing an embedded developer, who is considering the selection of an OS: 1. Does the design need an operating system at all? Some designs might appear... » read more

Embracing ISO 26262: Efficient Verification Of Safety-Critical Hardware
By OneSpin Solutions - 24 May, 2017 - Comments: 0

Automotive technology has come a long way since the days of the Ford Model T. Today's smart vehicles not only assist their drivers with tasks such as parking, lane management, and braking, but also function as a home away from home, with WiFi hotspots and sophisticated entertainment systems. All of these features have been made possible by increasingly complex electronic systems. Welcome though... » read more

Avoiding The Top 10 Software Security Design Flaws
By Synopsys - 24 May, 2017 - Comments: 0

Half of the software-related security defects that provide entry to threat agents are not found in buggy code – they are flaws embedded in software design. The IEEE Center for Secure Design brought together some of the foremost experts in software security in a working group to tackle the issue of secure software design. This whitepaper covers their findings. Find out why so many design... » read more

Whatever Happened To HLS?
By Brian Bailey - 24 May, 2017 - Comments: 1

A few years ago, [getkc id="105" comment="high-level synthesis"] (HLS) was probably the most talked about emerging technology that was to be the heart of a new [getkc id="48" kc_name="Electronic System Level"] (ESL) flow. Today, we hear much less about the progress being made in this area. Semiconductor Engineering sat down to discuss this with Bryan Bowyer, director of engineering for high-lev... » read more

Choosing The Right Verification Technology For CDC-Clean RTL Signoff
By Cadence - 24 May, 2017 - Comments: 0

Modern system-on-chip (SoC) designs typically contain multiple asynchronous clock domains. Clock domain crossing (CDC) signals, those which traverse these domains, are often subject to metastability effects that can cause functional errors. Traditional methods like RTL simulation or static timing analysis alone are not sufficient to verify correct data transfer across clock domains. As a result... » read more

Blog Review: May 24
By Jesse Allen - 24 May, 2017 - Comments: 0

Mentor's Andrew Patterson questions who should have control over who sees the vast amounts of data generated by automobiles and how it is used. In a series of posts, Cadence's Meera Collier considers philosophical questions from the angle of computer science. Synopsys' Eric Huang has a lighthearted look at today's world of robots. Rambus' Aharon Etengoff points to Director of National ... » read more

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