The Week In Review: Design


Tools Mentor Graphics launched the company's third generation data-center friendly emulation platform, Veloce Strato. The emulator has a capacity of 2.5BG when fully loaded, and total capacity can be increased by linking emulators. It has available slots for 64 Advanced Verification Boards (AVBs) and fully loaded consumes up to 50KW (22.7 W/Mgate) of power. Aldec uncorked the latest versi... » read more

Blog Review: Feb. 15


Mentor's Jean-Marie Brunet looks at factors driving the growth of hardware emulation for SoCs. Cadence's Dave Pursley asserts that the role of hardware developers is about to change for the better. Synopsys' Robert Vamosi says that major software vulnerabilities are becoming less frequent, in spite of hype surrounding named bugs. ARM's Rhonda Dirvin discusses the release of the OpenFog... » read more

System Bits: Feb. 14


Potential anticancer drugs selected by neural network Moscow Institute of Physics and Technology researchers along with Mail.Ru Group, and Insilico Medicine have applied a generative neural network to create new pharmaceutical medicines with certain desired characteristics. A generative adversarial network (GAN) was developed and trained to "invent" new molecular structures in order to dram... » read more

The Week In Review: Design


IP Rambus unveiled High Bandwidth Memory (HBM) Gen2 PHY developed for GlobalFoundries' FX-14 ASIC platform. The PHY, targeted at networking and data center applications, is fully compliant with the JEDEC HBM2 standard and supports data rates up to 2000 Mbps per data pin, for a total bandwidth of 256 GB/s. Omnitek launched a number of new FPGA-based video IPs, including HDMI2.0 Tx and Rx, ... » read more

Blog Review: Feb. 8


Mentor's Craig Armenti looks at some of the challenges involved with multi-board PCB or system design. Cadence's Paul McLellan highlights a presentation by Igor Keller on the state of the art in static timing analysis. Synopsys' Eric Huang has some ideas for USB interoperability testing. Intel's Ron Wilson delves into the current state of 5G, and why perspectives on that differ. Ans... » read more

System Bits: Feb. 7


Large scale quantum computer blueprint An international team comprised of researchers from the University of Sussex, Google, Aarhus University, RIKEN, and Siegen University recently unveiled what they say is the first practical blueprint for how to build a quantum computer. The team asserted that once built, the computer would have the potential to answer many questions in science; create n... » read more

The Week In Review: Design


Tools Synopsys announced the latest version of its VCS functional verification solution, which integrates native fine-grained parallelism (FGP) and additional engine optimizations for simulation on existing x86 CPU server configurations. Aldec released the latest version of its requirements lifecycle management solutions for FPGAs/SoCs, adding certification document templates and review c... » read more

Blog Review: Feb. 1


Synopsys' Anand Thiruvengadam investigates the challenges and tradeoffs that come with different abstraction models and use models in mixed-signal verification. Cadence's Paul McLellan highlights 16 big questions facing autonomous cars, from a presentation by Andreessen-Horowitz's Frank Chen. Mentor's Colin Walls says that when it comes to free stuff, keep an eye out for the real cost. ... » read more

Software Modeling Goes Mainstream


Software modeling is finally beginning to catch on across a wide swath of chipmakers as they look beyond device scaling to improve performance, lower power, and ratchet up security. Software modeling in the semiconductor industry historically has been associated with hardware-software co-design, which has grown in fits and starts since the late 1990s. The largest chipmakers and systems compa... » read more

System Bits: Jan. 31


Optimizing code To address the issue of code explicitly written to take advantage of parallel computing usually losing the benefit of compilers’ optimization strategies, MIT Computer Science and Artificial Intelligence Laboratory researchers have devised a new variation on a popular open-source compiler that optimizes before adding the code necessary for parallel execution. Charles E. Lei... » read more

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