category: System-Level Design

category: Auto, Security & Edge AI

Advanced ASICs Are A Team Sport
By Mike Gianfagna - 23 Feb, 2017 - Comments: 0

The recent Super Bowl proved that a team with conviction and focus can do anything. This notion comes in handy when you think about the nearly impossible job of designing and manufacturing an advanced ASIC – in finFET technologies, with an interposer, multiple die, and never-before-proven throughput rates. For these kind of advanced technologies, it does take a village. What works is open, tr... » read more

What Does AI Really Mean?
By Ed Sperling - 23 Feb, 2017 - Comments: 0

Seth Neiman, chairman of eSilicon, founder of Brocade Communications, and a board member and investor in a number of startups, sat down with Semiconductor Engineering to talk about advances in AI, what's changing, and how it ultimately could change our lives. What follows are excerpts of that conversation. SE: How far has AI progressed? Neiman: We’ve been working with AI since the mid 1... » read more

Fault Simulation Reborn
By Brian Bailey - 23 Feb, 2017 - Comments: 0

Fault simulation, one of the oldest tools in the EDA industry toolbox, is receiving a serious facelift after it almost faded from existence. In the early days, fault simulation was used to grade the quality of manufacturing test vectors. That task was replaced almost entirely by [getkc id="173" comment="scan test"] and automatic test pattern generation (ATPG). Today, functional safety is cau... » read more

Does Hardware/Software Verification Have To Be Broad And Deep? Check Out DVCon 2017
By Frank Schirrmeister - 23 Feb, 2017 - Comments: 0

DVCon 2017 is upon us next week and even though it is called the “Design and Verification” conference, it is rising more and more to the system level. One of the aspects of interest is how verification seems to simultaneously become broader—covering more aspects to verify like software, power and performance—while also becoming more deep when it comes to application domains and their sp... » read more

Find Your Way To San Jose Next Week… For DVCon, Of Course!
By Dave Kelf - 23 Feb, 2017 - Comments: 0

If you’re asked “Do you know the way to San Jose?” in the next few days, chances are it’s a newbie to DVCon. Everyone else in chip design verification knows the way to the annual Design and Verification Conference and Exhibition about to convene at the San Jose DoubleTree Hotel. This year’s program is stacking up to be an insightful and educational four days of tutorials, paper ses... » read more

The Path To (Virtually) Zero Defective Parts Per Million
By Synopsys - 22 Feb, 2017 - Comments: 0

Despite thorough wafer and package testing, a small number of defective ICs can make their way into systems. These test "escapes" often return as field failures, increasing costs and eroding profit margins. They can also present a hazard if deployed in safety-critical systems, which is why companies purchasing semiconductors for automotive, medical, or aerospace applications often demand a zero... » read more

IP Qualification with Oasys-RTL
By Mentor, a Siemens Business - 22 Feb, 2017 - Comments: 0

With increasing design sizes and complexities, the use of IP (intellectual property) as basic building blocks for better SoC design is also increasing. This paper presents the challenges faced during IP integration at the SoC level and what can be done to mitigate those risks during IP development. Mentor’s Oasys-RTL RTL floorplanning and physical synthesis tool offers a unique IP qualificati... » read more

Massive SoC Designs Open Doors To New Era In Simulation
By Cadence - 22 Feb, 2017 - Comments: 0

As system-on-chip (SoC) designs have grown in size, simulation technologies have had to evolve dramatically to keep pace. We’re now at an inflection point where both speed and capacity are essential and new simulation technologies are needed to meet the demands. In this paper, we’ll discuss how simulation has evolved and examine how new technologies such as the Cadence RocketSimTM Parallel ... » read more

Blog Review: Feb. 22
By Jesse Allen - 22 Feb, 2017 - Comments: 0

Mentor's Brian Derrick digs into the state of the electric vehicle industry and whether established OEMs will be able to make the changes required to meet new consumer demands. Cadence's Paul McLellan listens in on how to greatly improve the efficiency of machine learning, without using custom hardware, in a talk by Stanford's Kunle Olukotun. Synopsys' Robert Vamosi warns not to overlook ... » read more

System Bits: Feb. 21
By Ann Mutschler - 21 Feb, 2017 - Comments: 0

Recreating the brain Stanford University and Sandia National Laboratories researchers have created an organic, high-performance, low-energy artificial synapse for neural network computing that aims to better recreate the way the human brain processes information, and could also lead to improvements in brain-machine technologies. Alberto Salleo, associate professor of materials science and e... » read more

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