category: System-Level Design

category: Auto, Security & Edge AI

Uncertainty Rocks Chip Market
By Ed Sperling - 30 Jun, 2016 - Comments: 1

The semiconductor industry is undergoing sweeping changes in every direction, making it far more difficult to figure out which path to take next, when to take it, and how to get there. The next few years will redefine which semiconductor companies emerge as leaders, which ones get pushed down or out or absorbed into other companies, and which markets will be the most lucrative. And that coul... » read more

From Game Theory To The Unified Theory of Coherency
By Rajesh Ramanujam - 30 Jun, 2016 - Comments: 0

Adam Smith said that the best result comes from everyone in the group doing what is best for himself. But he’s only half right because the best result would come from everyone in the group doing what is best for himself and the group. If you are wondering where you might have heard this before, it was Russell Crowe playing John Nash in the movie “A Beautiful Mind.” John Nash was an Ame... » read more

Electrical-Mechanical Tool Flow Revisited
By Ann Mutschler - 30 Jun, 2016 - Comments: 0

For many years, the design tool industry has entertained the idea of combining both electrical and mechanical design into a single user experience, with a single database as a foundation. Major tool vendors, at least on the electrical side, have taken the matter seriously and confirm that activities towards a single flow have been considered, particularly as the [getkc id="7" kc_name="EDA"] ... » read more

Digging Into Trace Data
By Matt Sealey - 30 Jun, 2016 - Comments: 1

In previous blogs we covered an introduction to System Trace Macrocell (STM) concepts and terminology, and the STM Programmers' model with an example of how to generate efficient trace data. Once the STM is generating a trace stream, we may wish to view it within our Debugger. DS-5 implements an "Events View," which serves this purpose. Configuring your target First, it is necessary to... » read more

Improve DFT Verification And Meet Time-To-Market Goals With Emulation
By Steve Dondershine - 30 Jun, 2016 - Comments: 0

What if all the DFT verification on your next big chip could be completed before tape-out? This “shift-left” of DFT verification would eliminate the need for shortcuts in verification and allow for more types of verification. The benefits of faster and earlier DFT verification include higher confidence in the “golden” RTL, eliminating DFT from the critical path of tape-out, and more pre... » read more

Can Verification Meet In The Middle?
By Brian Bailey - 30 Jun, 2016 - Comments: 0

Since the dawn of time for the EDA industry, the classic V diagram has defined the primary design flow. On the left hand side of the V, the design is progressively refined and partitioned into smaller pieces. At the bottom of the V, verification takes over and as you travel up the right-hand side of the V, verification and integration happens until the entire design has been assembled and valid... » read more

Will Open-Source Work For Chips?
By Brian Bailey - 30 Jun, 2016 - Comments: 2

Open source is getting a second look by the semiconductor industry, driven by the high cost of design at complex nodes along with fragmentation in end markets, which increasingly means that one size or approach no longer fits all. The open source movement, as we know it today, started in the 1980s with the launch of the GNU project, which was about the time the electronic design automation (... » read more

Reducing Design Risk With Testbench Acceleration
By Mentor, a Siemens Business - 29 Jun, 2016 - Comments: 0

Part 1 in a series of papers that demystify the performance of SystemVerilog and UVM testbenches when using an emulator for the purpose of hardware-assisted testbench acceleration. In these three papers, architectural and modeling requirements are described, followed by a recommended systematic approach for maximizing overall testbench acceleration speed-up and achieving your ultimate performan... » read more

ISO 26262-Certified Solution For Testing of Safety-Critical Automotive ICs
By Synopsys - 29 Jun, 2016 - Comments: 0

Anti-lock braking systems, air bags, traction control, and electronic stability control are just a few examples of typical safety systems in current production cars. Next-generation safety systems, known as Advanced Driver Assistance Systems, or ADAS, are setting up the path for semi- and fully autonomous cars of the near future. Some ADAS technology uses a combination of cameras and radar to s... » read more

Achieving 100% Functional Coverage By Operational Assertion-Based Verification
By OneSpin Solutions - 29 Jun, 2016 - Comments: 0

This white paper presents Operational Assertion-Based Verification (ABV), an advanced formal verification methodology resulting in a predictable, small number of high-level assertions capturing the functionality of a design. Operational ABV enables an automatic formal coverage analysis, which identifies holes in verification plans, unverified design functionality as well as errors and omissio... » read more

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