Aldec HES Emulation Integration With Imperas OVP


Virtual platforms play a significant role in system level development, but require the speed that emulation systems provide for hardware/software co-verification. This white paper describes a high performance virtual modeling solution achieved by integrating Aldec’s Transaction Level Emulation System with Imperas’ OVP (Open Virtual Platform) and OVPsim (OVP simulator). Hardware and Software... » read more

Blog Review: June 29


Ansys' Justin Nescott checks out the world's first electric highway for trucking in this week's top five tech picks. Plus, some cool houses, Boston Dynamics' giraffe-bot, and a drum kit in a backpack. Applied's Matt Cogorno takes a look at the challenges facing etch methods as devices keep getting smaller. Synopsys' Apoorva Mathur digs into the energy efficient aspects of the MIPI M-PHY a... » read more

Top Mobile OEM Uses NetSpeed to Boost Its Next Gen Application Processor


The smartphone segment is certainly the most competitive market for chip makers today and the yearly product launch cadence puts a lot of pressure on the application processor design cycle. End-users expect to benefit from higher image definition, better sound quality, ever faster and more complex applications which push the limits of application processor performance in terms of higher frequen... » read more

System Bits: June 28


Deep-learning-based virtual reality tool Given that future systems which enable people to interact with virtual environments will require computers to interpret the human hand’s nearly endless variety and complexity of changing motions and joint angles, Purdue University researchers have created a convolutional neural network-based system that is capable of deep learning. [caption id="att... » read more

The Week In Review: Design


Tools & IP Synopsys uncorked PHY and Controller IP for PCI Express 4.0 architecture, which the company says reduces latency by up to 20% and area by 15% compared to the previous implementation. The IP supports lane margining to assess performance variation tolerance. PLDA announced a PCIe 4.0 development platform, and provides a PCIe 3.0-x8 (upstream) to PCIe 4.0-x4 (downstream) Integ... » read more

Blog Review: June 22


A Lam Research writer investigates the challenges that lie ahead for interconnects and whether current technologies will find new life or be replaced by new strategies. There's a greater force powering Moore's Law, says Cadence's Paul McLellan, who points to the vast amount of transistors being used for memory. Mentor's Robert Bates considers the challenges of securing in-hospital network... » read more

System Bits: June 21


Faster running parallel programs, one-tenth the code MIT researchers reminded that computer chips have stopped getting faster and that for the past 10 years, performance improvements have come from the addition of cores. In theory, they said, a program on a 64-core machine would be 64 times as fast as it would be on a single-core machine but it rarely works out that way. Most computer programs... » read more

The Week In Review: Design


Tools Synopsys uncorked the latest version of its software for the design of optical communication systems and photonic integrated circuits at the signal propagation level, adding a new interface and expanding the software's application design libraries. Mentor Graphics said it would provide a variety of tools to support the new Zynq UltraScale+ MPSoC devices from Xilinx, dual-core field-... » read more

System-Level Verification Tackles New Role


Semiconductor Engineering sat down to discuss advances in system-level verification with Larry Melling, product management director for the system verification group of [getentity id="22032" e_name="Cadence"]; Larry Lapides, vice president of sales for [getentity id="22036" e_name="Imperas”] and Jean-Marie Brunet, director of marketing for the emulation division of [getentity id="22017" e_nam... » read more

Blog Review: June 15


Synopsys' Marc Greenberg shares a somber and personal story on the need to get ADAS to as many drivers as possible. From the Linley IoT conference, Cadence's Paul McLellan features a talk on protecting edge nodes and the three big steps towards IoT security. Mentor's Avidan Efody presents a lighthearted reminder on the basics of ISO 26262 terminology. Just how much security is enough? ... » read more

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