Hybrid Emulation Gets More Hybrid


Rising chip complexity is creating a booming emulation business, as chipmakers working at advanced nodes turn to bigger iron to get chips out the door on time. What started as a "shift lift"—doing more things earlier in the design cycle—is evolving into a more complex mix of hardware-accelerated verification for both hardware and software. There are even some new forays into power explor... » read more

Culture Clash In Analog


The analog/mixed signal world is being shaken up by a mix of new tools, an influx of younger engineers with new and broader approaches, and an emphasis on changing methodologies to improve time to market. Analog and digital engineers have never quite seen eye-to-eye. Analog teams leverage techniques that have been around, in some cases, for decades, while digital teams rely heavily on the la... » read more

The New Face Of Formal


Semiconductor Engineering sat down to discuss the recent growth in adoption of formal technologies and tools with Lawrence Loh, product engineering group director at [getentity id="22032" e_name="Cadence"], Praveen Tiwari, senior manager of R&D in the verification group at [getentity id="22035" e_name="Synopsys"], Harry Foster, chief scientist at [getentity id="22017" e_name="Mentor Graphic... » read more

Say Hi To Hybrid


It has been proposed for some time that virtual platforms could be linked to emulation hardware in order to co-verify the software and hardware components of an SoC. However, that proposal now has evolved into hybrid emulation, a practical solution to allow pre-silicon verification and validation of today’s complex SoC designs. First-rate work by the standards body Accellera and the Open ... » read more

3D Thermal Simulation Of Resistive Heating


Joule heating, also known as resistive or Ohmic heating, is the power lost to heat as electrical current flows down a conductor. We were introduced to Joule’s first law (Power dissipation = I²R, VI, V²/R) way back in high school. From an electronics thermal simulation perspective it requires a full 3D electrical flow simulation to be conducted, and from that the Joule heating power dissipat... » read more

Requirements For Datacenter-Ready Emulation


It’s time to look at what the latest trends in emulation are and to review some of the key requirements to make it datacenter-ready. Specifically, I will look at virtualization of external interfaces as well as emulation throughput, specifically the allocation of jobs into emulators. One overarching trend in verification lies in the connection of the engines in what Jim Hogan has dubbed t... » read more

Top 5 Reasons The SoC Interconnect Matters


The on-chip interconnect is the one area of SoC design that still does not receive the priority that it deserves. It’s like Rodney Dangerfield: It gets no respect. However, that is changing because of rising chip complexity, smaller process dimensions, and acknowledgement of the fact that in a world where design teams commercially license most of the chip’s critical semiconductor IP (like C... » read more

Technology Reboot Required


The International Technology Roadmap for Semiconductors (ITRS) has produced reports outlining the major obstacles the electronics industry faces for a long time now. It attempts to project, with a 15-year horizon, the problems that need to be solved in order to take advantage of the complete design and manufacturing ecosystem. From this, early research efforts can be started. This enabled the E... » read more

You Can’t Walk Straight Blindfolded


Let’s examine the first part of the title of this blog. It is stated as a given. But is it true that you really can’t walk straight when blindfolded? That is what my children and I set out to investigate one sunny afternoon in October (yes we live in California). We looked for a nice open field with little to no surrounding sound, so that you cannot use the sound to set your bearing. We ... » read more

10 Common Device Noise Analysis Mistakes


Device noise is critical in nanometer-scale CMOS processes, and it fundamentally limits the performance of many circuits at 45 nm and below. Given the right tools, device noise analysis (DNA) is a fairly straightforward process that should produce results that are within 1 dB to 2 dB of silicon measurements. However, there are a number of common mistakes that can lead to grossly overestimating ... » read more

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