category: System-Level Design

category: Auto, Security & Edge AI

The Week In Review: Design
By Ed Sperling - 03 Oct, 2014 - Comments: 0

IP ARM introduced a new software platform and a free operating system aimed at IoT development. The OS incorporates security, communication and device management features for improved energy efficiency. The device server simplifies the connection and management of devices, incorporating security and improving efficiency. Cadence rolled out a broad IP portfolio for TSMC's 16nm platform, and ... » read more

More Than Moore
By Ed Sperling - 01 Oct, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the value of feature shrinks and what comes next with Steve Eplett, design technology and automation manager at [getentity id="22664" e_name="Open-Silicon"]; Patrick Soheili, vice president and general manager of IP Solutions at [getentity id="22242" e_name="eSilicon"]; Brandon Wang, engineering group director at [getentity id="22032" e_name="Cadenc... » read more

Blog Review: Oct. 1
By Ed Sperling - 01 Oct, 2014 - Comments: 0

Cadence's Richard Goering writes about a pair of IEEE working groups that are focused on standardizing ways to lower power of software and firmware. The importance of this effort is huge. Mentor's J. VanDomelen looks at the use of 3D printers in outer space. This is a new chapter in manufacturing custom parts in extreme environments. Synopsys' Mick Posner gets an unexpected answer to a ro... » read more

System Bits: Sept. 30
By Ann Mutschler - 30 Sep, 2014 - Comments: 0

Airway muscle-on-a-chip mimics asthma A Harvard University research team has developed a human airway muscle-on-a-chip that could be used to test new drugs as it accurately mimics the way smooth muscle contracts in the human airway, under normal circumstances and when exposed to asthma triggers. The chip also gives a window into the cellular and even subcellular responses within the tissue ... » read more

Where Do We Stand With CDC
By Ann Mutschler - 29 Sep, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss where the industry stands on clock domain crossing with Charlie Janac, CEO of [getentity id="22674" e_name="Arteris"]; Shaker Sarwary, VP of Formal Verification Products at [getentity id="22026" e_name="Atrenta"]; Pranav Ashar, CTO at [getentity id="22416" e_name="Real Intent"]; and Namit Gupta, CAE, Verification Group at [getentity id="22035" e_nam... » read more

Tech Talk: IP Integration
By Ed Sperling - 27 Sep, 2014 - Comments: 0

Sonics CTO Drew Wingard talks about the challenges of integrating IP into SoCs and what typically goes wrong. [youtube vid=T1FAPDqIJK8] » read more

The Real Numbers: Redefining NRE
By Ed Sperling - 26 Sep, 2014 - Comments: 0

Developing ICs at the most advanced nodes is getting more expensive, but exactly how much more expensive is the subject of debate across the semiconductor industry. There are a number of reasons for this discrepancy. Among them: As design flows shift from serial to parallel, it's hard to determine which groups within companies should be saddled with different portions of the bill. The re... » read more

‘Hardening’ SoCs For Automotive Market Challenges
By Kurt Shuler - 26 Sep, 2014 - Comments: 0

The semiconductor is enamored with the automotive, industrial and medical markets, and many companies are now shifting their focus there. But many mainstream vendors will face challenges entering this market. For those who have traditionally participated in the smart phone or mobility market, I will outline some changes they need to consider to successfully compete in these emerging spaces. ... » read more

The Week In Review: Design
By Ed Sperling - 26 Sep, 2014 - Comments: 0

Tools Synopsys rolled out a hybrid verification platform, which it said can shave months off design time. The platform acts like a bridge between emulation, FPGA prototyping, simulation, static and formal verification and debug. Mentor Graphics uncorked a new version of its embedded hypervisor, which includes better system configuration, debugging and hardware support. The hypervisor is aim... » read more

Which Comes First?
By Ed Sperling - 25 Sep, 2014 - Comments: 0

Methodologies in IC design typically follow tools. The tools enable the methodologies, and chipmakers' businesses are built around both of them. That has been the rock-solid foundation for the design and production of chips since well before the impenetrable 1-micron wall. But that approach is falling apart at 28nm, and it will continue to crumble at 16/14nm and 10nm. It simply isn't fast en... » read more

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