Taking Aim At Big Data


By Ed Sperling As the Internet of Things bridges the gap between the mobile and big data worlds, EDA and IP vendors increasingly are looking well beyond their usual boundaries. How successful they are at moving upward into a market that is far less price-sensitive remains to be seen. But from a technology standpoint, at least, the issues encountered by data centers and cloud providers are ... » read more

Design Topology Requires Physical Data


By Ann Steffora Mutschler To best understand a design topology and make decisions on clock/register gating, vector sets are required for the RTL tools to understand how to gate clocks and registers. However, if certain constraints are set on all enabled signals in RTL they can be re-used for gating clocks and registers downstream where enablers are not available—even without needing a ... » read more

Experts At The Table: The Internet Of Everything


By Ed Sperling System-Level Design sat down to discuss the Internet of Things with Jack Guedj, president and CEO of Tensilica; John Heinlein, vice president of marketing for the physical IP division of ARM; Kamran Izadi, director of sourcing and supplier management at Cisco; and Oleg Logvinov, director of market development for STMicroelectronics’ Industrial and Power Conversion Division. Wh... » read more

Reducing Wait Time


By Tom De Schutter Last month we were all waiting for white smoke to emerge from the chimney on the roof of the Sistine Chapel at the Vatican. I am of course talking about the election of the new pope. I couldn’t help but see a parallel with how software developers are anxiously waiting for their software to run correctly and finally get past the series of seemingly never ending bugs (black ... » read more

Unknown Signoff


In last month’s blog, Pranav Ashar, CTO at [getentity id="22416" e_name="Real Intent"], pointed out that the management of unknowns (X’s) in simulation has become a separate verification concern of signoff proportions. Modern power management schemes affect how designs are reset (start). X management and reset analysis are interrelated because many of the X’s in simulation come from unini... » read more

The Analyst View


By Kurt Shuler I was fortunate to be able to meet with 13 different semiconductor industry analysts from eight different companies over the last two weeks. Our conversations ranged from the current state of the semiconductor industry to future software architecture trends. I want to take this opportunity to thank them once again for the exchange of ideas and the opportunity to learn from them.... » read more

The Power Treadmill


By Frank Ferro The recent purchase of an LTE smart phone has me back on my power management soapbox. I upgraded my phone about a month ago to the newest version (staying with the same manufacturer as my previous device) and to my dismay, although it wasn’t completely unexpected, the battery life was actually shorter. I did not do a ‘scientific’ comparison, but following the same daily us... » read more

Simple Economics


By Jon McDonald I was watching one of the MIT OpenCourseWare videos the other day. It was one of the lectures on Computer Science. I believe it was Prof. Robert Gallager who made a statement that really got me thinking: “Increasingly, system computational complexity has little impact on cost because of chip technology.” From a hardware perspective I initially had a bit of trouble with t... » read more

The Next Big Thing


The “next big thing” is always a collection of things—technologies that come together at the right moment to produce a wildly popular new product at a time when the market can consume it, build on it and truly recognize and leverage its value. What’s different about the Internet of Things is that, despite efforts to take control of it, there is no single owner, no company or even gr... » read more

Using Power Aware IBIS v5.0 Behavioral IO Models To Simulate Simultaneous Switching Noise


Typically simultaneous switching noise (SSN) transient simulations require significant CPU and RAM resources. A prominent factor affecting both CPU and RAM resource requirements is the number of MOSFET models included in the post layout extracted IO netlists. By replacing the IO netlists with power aware IBIS v5.0 behavioral models, both the CPU and RAM resource requirements are dramatically re... » read more

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