category: System-Level Design

category: Auto, Security & Edge AI

Clock Domain Crossing Demystified
By Various Writers - 25 Apr, 2013 - Comments: 0

A look at the second-generation solution for CDC verification. To download this white paper, click here. » read more

Virtual Prototypes: When, Where And How To Use Them
By Various Writers - 25 Apr, 2013 - Comments: 0

An innovation-hungry public and a highly competitive marketplace make for short product cycles, while the sophistication and performance expected of digital devices grows with every new product generation. Heterogeneous multiprocessing, where different cores do specialized work, has become the industry norm inside those devices, radically increasing the amount of software needed, the importance... » read more

Communicate, eXecute And Translate, Oh My!
By Various Writers - 25 Apr, 2013 - Comments: 0

This paper describes a model-driven development approach that leverages modeling efforts to validate functionality and transform high level models into forms that are useful at the next development step. It includes an example of one company's motivations for adopting such an approach, the methodology they adopted, and the value they found in using an MDD flow. To download this white paper,... » read more

Experts At The Table: Verification Nightmares
By Ed Sperling - 23 Apr, 2013 - Comments: 0

By Ed Sperling Low-Power Engineering sat down with Shabtay Matalon, ESL marketing manager in Mentor Graphics’ Design Creation Division; Bill Neifert, CTO at Carbon Design Systems; Terrill Moore, CEO of MCCI Corp., and Frank Schirrmeister, director of product marketing for system-level solutions at Synopsys. What follows are excerpts of that conversation. LPE: Where does power fit in? N... » read more

Subsystems And Reuse
By Frank Schirrmeister - 23 Apr, 2013 - Comments: 0

By Frank Schirrmeister The last couple of weeks have been very busy with travel, customer meetings and presentations—DATE in Grenoble, CDNLive in San Jose and, most recently, EDPS in Monterey. Software enablement and IP sub-systems have been the key themes throughout these events, and during Gary Smith’s keynote at EDPS, I realized that subsystem reuse may be a significant step to solving ... » read more

x86 Processor Road Map No Longer Just About Speed
By Ed Sperling - 01 Apr, 2013 - Comments: 0

By Ed Sperling The decades-old approach of powerful processors with ever-faster clock speeds is changing. Performance matters in some settings, but the real concern is adding more functionality within power budgets. The most pressing tradeoff is now performance vs. power, which has forced processor architects at AMD, Intel and IBM to take into account everything from application software to... » read more

Experts At The Table: Verification Strategies
By Ed Sperling - 28 Mar, 2013 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss verification strategies and changes with Harry Foster, chief verification scientist at Mentor Graphics: Janick Bergeron, verification fellow at Synopsys; Pranav Ashar, CTO at Real Intent; Tom Anderson, vice president of marketing at Breker Verification Systems; and Raik Brinkmann, president and CEO of OneSpin Solutions. What follows are e... » read more

Diverging Viewpoints
By Ed Sperling - 28 Mar, 2013 - Comments: 0

By Ed Sperling The raw materials of semiconductor design include smart, well-trained people and money to fund good ideas from those people, whose backgrounds typically come from engineering, math, physics, computer science, materials science and sometimes even chemistry. While many experts, executives, and industry groups have been sounding the alarm in recent years about everything from la... » read more

Executive Briefing: Wally Rhines
By Ed Sperling - 28 Mar, 2013 - Comments: 0

By Ed Sperling System-Level Design, as part of its ongoing executive briefing series, sat down with Wally Rhines, Mentor Graphics' chairman and CEO, to talk about future problems, opportunities, and the gray areas that could go either way. What follows are excerpts of that conversation. SLD: Is the amount of time spent on verification increasing? Rhines: It depends on how you define who s... » read more

The Evolving Interconnect
By Ann Mutschler - 28 Mar, 2013 - Comments: 0

By Ann Steffora Mutschler Chip interconnect protocol requirements are evolving as designs move to 20nm and below process geometries, and not always in predictable ways. At least part of this is being driven by what an SoC is used for. The continued push to shrink features opens up real estate at each new process node. For the past decade, that real estate has been used to add more featu... » read more

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