category: System-Level Design

category: Auto, Security & Edge AI

Clock And Reset Ubiquity: A CDC Verification Perspective
By Various Writers - 28 Feb, 2013 - Comments: 0

Today’s SoC integrates a collection of peripherals, memory, graphics, networking and I/O components that originate from a multitude of sources. It could comprise designs from within the company, from other companies or from third-party IP vendors. These independently developed components come together to enable a rich feature set for the SoC. However, accompanying this abundance of features i... » read more

Chip Economics
By Various Writers - 28 Feb, 2013 - Comments: 0

The concise research paper, "NoC Interconnect Improves SoC Economics: Initial Investment is Low Compared to SoC Performance and Cost Benefits," by Objective Analysis Semiconductor Market Research, provides quantitative data from user experiences comparing the costs and benefits of implementing network on chip SoC interconnects versus traditional bus and crossbar interconnects. You will learn... » read more

Ready For 3D-IC
By Various Writers - 28 Feb, 2013 - Comments: 0

This technical presentation describes the challenges and Mentor's solutions for verifying and testing IC designs targeted for 3D packages, such as stacked die using TSVs or multi-die packages using silicon interposers. To download this white paper, click here. » read more

Development Tools Enabling The Internet of Things
By Frank Schirrmeister - 27 Feb, 2013 - Comments: 0

I'm at the Embedded World conference in Nuremberg this week. Yes, between Mobile World Congress in Barcelona and DVCon in San Jose, Calif., I chose Embedded World. Unfettered by unseasonally late snow and bad weather, it turns out this was the right decision. I have not attended this show for a couple of years and am pleased to find that the show has developed quite a bit. There are more than 8... » read more

Verifying Complex Chips
By Ed Sperling - 27 Feb, 2013 - Comments: 0

System-Level Design talks about what's changing in SoC verification with Janick Bergeron, verification fellow at Synopsys; Harry Foster, chief verification scientist at Mentor Graphics; Pranav Ashar, chief technology officer at Real Intent; Raik Brinkmann, president and CEO of OneSpin Solutions, and Tom Anderson, vice president of marketing at Breker Verification Systems. [youtube vid=DzDYyf... » read more

Inflection Points And Changes Ahead
By Ed Sperling - 23 Feb, 2013 - Comments: 0

It’s hard to justify throwing away a well-oiled machine and replacing it with a new one. It works, it’s predictable and it’s low risk. And nowhere is this more evident than in the semiconductor industry. The doubling of transistors every two years for nearly five decades has created a $300 billion chip industry, reduced the price of processing by orders of magnitude, and made possible ele... » read more

SoC Architects Face Big Challenges
By Ed Sperling - 31 Jan, 2013 - Comments: 0

By Ann Steffora Mutschler While the geometries of advanced node processes such as 28nm and below may not greatly impact SoC architectures, the complexity enabled by the leading edge brings intense challenges all the same. With the ability to put more transistors onto a chip come new possibilities such as the increasing use of multi-core architectures and lots of integrated hardware en... » read more

Inside The System-Level Supply Chain
By Ed Sperling - 31 Jan, 2013 - Comments: 0

System-Level Design sat down to discuss supply chain issues with Bill Chown product marketing director for the system-level engineering division at Mentor Graphics and a longtime participant in a number of standards efforts across the semiconductor design industry. What follows are excerpts of that conversation. SLD: What’s happening with system engineering as chip design/manufacturing mo... » read more

Mixing It Up
By Ed Sperling - 31 Jan, 2013 - Comments: 0

By Ann Steffora Mutschler To enable the next level of productivity in the verification space, certain tools need to be combined and integrated in a very meaningful way. The concept is far from new. This happened on the RTL to GDS front between synthesis and place and route. The tools work very closely and there is bi-directional collaboration. It also happened in the functional verification... » read more

Cost Per Transistor Gets Fuzzier
By Ed Sperling - 31 Jan, 2013 - Comments: 0

By Ed Sperling Cost per transistor always has been a major reason for chipmakers to migrate to the next process node. By shrinking transistors and adding more logic, performance usually gets a boost. Moreover, that usually provides enough engineering wiggle room to add some improvements in energy efficiency. The basic assumption that you can double the number of transistors every 24 months,... » read more

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