category: System-Level Design

category: Auto, Security & Edge AI

The Rise Of Layout-Dependent Effects
By Ann Mutschler - 28 Feb, 2013 - Comments: 0

By Ann Steffora Mutschler Designing for today’s advanced semiconductor manufacturing process nodes brings area, speed, power and other benefits but also new performance challenges as a result of the pure physics of running current through tiny wires. Layout-dependent effects (LDE), which emerged at 40nm and are having a larger impact at 28 and 20nm, introduce variability to circuit ... » read more

Surprises Abound As Subsystem IP Gains Prominence
By The SE Staff - 28 Feb, 2013 - Comments: 0

What’s new in the world of subsystem intellectual property? To find out, System-Level Design sat down with Richard Wawrzyniak, senior market analyst for ASICs and SoCs at Semico Research Corp. What follow are excerpts of that conversation. SLD: You mentioned that the cost of semiconductor intellectual property (IP) at 20nm and below is increasing. Why is that? Wawrzyniak: The reason is c... » read more

Experts At The Table: Verification Strategies
By Ed Sperling - 28 Feb, 2013 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss verification strategies and changes with Harry Foster, chief verification scientist at Mentor Graphics: Janick Bergeron, verification fellow at Synopsys; Pranav Ashar, CTO at Real Intent; Tom Anderson, vice president of marketing at Breker Verification Systems; and Raik Brinkmann, president and CEO of OneSpin Solutions. What follows are ex... » read more

Have You Had A V8 today?
By Nithya Ruff - 28 Feb, 2013 - Comments: 0

By Nithya Ruff The quick road to the recommended daily allowance of vegetables and fruits is often a bottle of V8. It’s quick, nutritious, and it makes us feel less guilty about any of our nutritional imbalances. It makes us feel virtuous, because we have done something good for our body today. So why do we postpone the inevitable? By this I mean developing new software for a new piec... » read more

Is This The Era Of Automatic Formal Checks For Verification?
By Graham Bell - 28 Feb, 2013 - Comments: 0

I was thinking about the above question and recalled something IBM would repeat annually back in the late 1980s about its OS/2 replacement for MS-DOS. “This is the year of OS/2!” they would shout. But the marketplace wasn’t listening. As one buddy of mine liked to say, it was only half of an operating system (O.S./2). In the last nine months, my company, Real Intent, along with our com... » read more

Advanced SoC Interconnect IP
By Kurt Shuler - 28 Feb, 2013 - Comments: 0

By Kurt Shuler I am thoroughly enjoying 2013. That’s because there seems to be a lot more reason for optimism this year than last year. But before we let go of 2012, it’s important to reflect on the past year and see what it can teach us so we can make better business decisions moving forward. The one lesson learned is that flexibility for SoC designs is increasingly more important. In ... » read more

Power Management: Throwing Down The Gauntlet
By Frank Ferro - 28 Feb, 2013 - Comments: 0

By Frank Ferro The recent burst of articles challenging smart phone battery life has me asking the question, “Are we ready to turn the corner on power consumption?” About two years ago I was bemoaning the fact that we are willing to live with a smart phone that gets only one day of battery life (Powering Forward or Moon Walking). As of today, nothing has changed. We still need to charge th... » read more

Modeling Errors
By Ed Sperling - 28 Feb, 2013 - Comments: 0

Raising the abstraction level in increasingly large and complex design requires proxies. In IC world, we think of them in terms of higher abstractions, but the basic premise is that you can’t focus on ever detail without losing sight of the bigger picture, so we build models that can represent those details. Done well, these models are incredibly useful. They save time, make it easier to ... » read more

Designing with FinFETs: The Opportunities and the Challenges
By Various Writers - 28 Feb, 2013 - Comments: 0

With the help of double-patterning and other advanced lithography techniques, CMOS technology continues to scale to 20-nanometer (nm) and beyond. Yet, because of their superior attributes, FinFETs are replacing planar CMOS technology as the device technology of choice at these advanced nodes. In particular, FinFETs demonstrate better results in the areas of performance, leakage and dynamic powe... » read more

Blocking Vs. Non-Blocking
By Various Writers - 28 Feb, 2013 - Comments: 0

By analyzing two flow control protocols – Single Threaded Tag (STT) and Multi-Threaded Non-Blocking – we describe a typical SoC employing the two protocols and evaluate their relative advantages and disadvantages. We evaluate the two protocols by experimentation with a representative digital TV (DTV) design and its derivatives, and then show you how one system is able to achieve better perf... » read more

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