category: System-Level Design

category: Auto, Security & Edge AI

Keeping Pace With Moore’s Law
By Ann Mutschler - 19 Dec, 2012 - Comments: 0

By Ann Steffora Mutschler As the number of transistors doubles with each move to a smaller manufacturing process technology, there are questions as to whether the current cadre of place and route tools will be able to keep in lock step. Have no fear, assured Saleem Haider, senior director of marketing for physical design and DFM at Synopsys. “For the increase in densities that we get with... » read more

Step On It
By Nithya Ruff - 19 Dec, 2012 - Comments: 0

By Nithya Ruff On a recent trip to Germany, I was a passenger in a car with my colleague Tom De Schutter on the German Autobahn. We had just landed in Frankfurt and were driving to Aachen, Germany. The anticipation of the potential speed at which we would drive created both excitement and anxiety in me. What I learned about driving on the Autobahn was eye opening with how Germany allows for sp... » read more

Clocks And Bugs
By Graham Bell - 19 Dec, 2012 - Comments: 2

In late September, I blogged about the results of the 2012 DAC survey on CDC bugs, X propagation, and timing constraints by Real Intent. Now for those of you who don't remember what CDC means, it is an acronym for clock domain crossing. In modern SoCs, the number of different clock domains can easily exceed 100, due to the integration of different blocks and IP, each with their own clock. Not ... » read more

The Network Is The SoC…
By Frank Ferro - 19 Dec, 2012 - Comments: 0

By Frank Ferro SoC design continues to challenge semiconductor and system companies in their pursuit to create a better user experience for a wide range of products. Given this, I was pleasantly surprised to see that two of the “Ten technologies that will change the world in 2013,” according to EETimes (December 2012 issue) were SoC-related. One is virtual SoC prototypes and the other i... » read more

Predictions, Problems And Prognosis
By Ed Sperling - 19 Dec, 2012 - Comments: 0

Never before in the long and often turbulent history of the semiconductor industry have so many problems presented themselves at each new process node. And never before have there been so many well-tested choices to resolving them. After possibly the most intensive, extensive and expensive research this industry has ever witnessed, Moore’s Law is now technologically assured down to at leas... » read more

On-Chip Communications Survey Results
By Various Writers - 19 Dec, 2012 - Comments: 0

This comprehensive report takes a closer look at general technology trends and factors associated with OCCNs, such as core target speeds. It investigates the most popular OCCN topologies being considered for implementation in multi-core SoCs, including networks-on-chip (NoCs), crossbars, peripheral interconnect, and multi-layer bus matrices. It then dives deeper into NoCs, including analyzing a... » read more

Automotive SoC Maker Uses NoC Technology
By Various Writers - 19 Dec, 2012 - Comments: 0

How the world's #1 vision-based Advanced Driver Assistance and Collision Avoidance Systems company uses Arteris FlexNoC interconnect IP to address demanding low-latency requirements in its automotive products. To download this white paper, click here. » read more

Addressing Today’s Complex Clock Modeling Issues With Veloce Emulation Technology
By Various Writers - 19 Dec, 2012 - Comments: 0

Earlier designs were smaller, less complex, and had simpler clocking. A few years back, verification was much easier and clock modeling was not such a big concern. With the drastic increase in the use of System-on-Chip (SoC), designs today are becoming extremely complex with an increasing number of peripherals/external interfaces to consider, requiring a higher numbers of asynchronous clocks. ... » read more

Challenges In Verification Of Clock Domain Crossings
By Various Writers - 19 Dec, 2012 - Comments: 0

Emerging systems have three dimensions of complexity when it comes to making them CDC-safe. First, the number of asynchronous clock domains in designs can range from the tens to the hundreds for complex systems with many components. Second, the master clock frequencies vary per component. It is not uncommon for the ratio between the fastest and the slowest clocks to be greater than 10. Third, t... » read more

TLM-Driven Design And Verification—Time For A Methodology Shift
By Various Writers - 19 Dec, 2012 - Comments: 0

While today’s RTL design and verification flows are a step up from the gate-level flows of two decades ago, RTL flows are straining to meet the demands of most product teams. When designs are sourced and verified at the register transfer level (RTL), IP reuse is difficult, functional verification is lengthy and cumbersome, and architectural decisions cannot be confirmed prior to RTL verificat... » read more

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