category: System-Level Design

category: Auto, Security & Edge AI

Cadence Cerebrus In SaaS And Imagination Technologies Case Study
By Cadence - 27 Mar, 2024 - Comments: 0

Artificial Intelligence (AI) has made noteworthy progress and is now ready and available for electronic design automation. The Cadence Cerebrus Intelligent Chip Explorer utilizes AI—specifically, reinforcement machine learning (ML) technology—combined with the industry-leading Cadence digital full flow to deliver better power, performance, and area (PPA) more quickly. However, this highl... » read more

Blog Review: Mar. 27
By Jesse Allen - 27 Mar, 2024 - Comments: 0

Cadence's Steve Brown suggests that multi-die technologies will be a key part of the path toward a faster, more efficient chip ecosystem that can support the compressed development cycles now emerging in the automotive industry. Synopsys' John Swanson, Madhumita Sanyal, and Priyank Shukla point to the role of simulation in ensuring seamless operation in the Ethernet ecosystem though rigorous... » read more

The Data Crisis Is Unfolding — Are We Ready?
By Alphawave Semi - 27 Mar, 2024 - Comments: 0

The rapid advancement of technology has led to an unprecedented amount of data being generated, captured, and consumed globally. However, this reliance on data comes at a considerable cost. The widespread sharing and processing of data is necessary to navigate our everyday lives. Still, any disruption to this process can have severe consequences, threatening our ability to function as a society... » read more

3D-IC Intensifies Demand For Multi-Physics Simulation
By Ann Mutschler - 20 Mar, 2024 - Comments: 0

The introduction of full 3D-ICs will require a simultaneous analysis of various physical effects under different workloads, a step-function change that will add complexity at every step of the design flow, expand and alter job responsibilities, and bring together the analog and digital design worlds in unprecedented ways. 3D-ICs will be the highest-performance advanced packaging option, in s... » read more

Blog Review: March 20
By Jesse Allen - 20 Mar, 2024 - Comments: 0

Synopsys' Kiran Vittal delves into AI chips, including the expansion of chip design beyond traditional semiconductor companies, adoption of RISC-V, and the use of formal equivalence checking to verify complex AI datapaths. Siemens' Patrick McGoff points to a survey that suggests projects deploying design for manufacturing within a PCB design flow are more likely to be completed on-time, on-q... » read more

Blog Review: Mar. 13
By Jesse Allen - 13 Mar, 2024 - Comments: 0

Cadence's Geeta Arora explains the Address Translation Service in PCIe 6.0, which allows an I/O device to perform its own virtual to physical address translations without relying on the host's CPU to reduce latency and improve overall system performance. Synopsys' John Swanson, Jon Ames, Priyank Shukla, and Varun Agrawal highlight the upcoming 1.6T iteration of the Ethernet standard and the ... » read more

Security Is Critical For Commercial Chiplets
By Ann Mutschler - 13 Mar, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to talk about the security issues and requirements in commercial chiplet ecosystem, with Frank Schirrmeister, vice president solutions and business development at Arteris; Mayank Bhatnagar, product marketing director in the Silicon Solutions Group at Cadence; Paul Karazuba, vice president of marketing at Expedera; Stephen Slater, EDA prod... » read more

Chiplet IP Standards Are Just The Beginning
By Ann Mutschler - 06 Mar, 2024 - Comments: 2

Experts at the Table: Semiconductor Engineering sat down to talk about chiplet standards, interoperability, and the need for highly customized AI chiplets, with Frank Schirrmeister, vice president solutions and business development at Arteris; Mayank Bhatnagar, product marketing director in the Silicon Solutions Group at Cadence; Paul Karazuba, vice president of marketing at Expedera; Stephen S... » read more

Blog Review: Mar. 6
By Jesse Allen - 06 Mar, 2024 - Comments: 0

Synopsys' Gandharv Bhatara notes that successfully deploying high-NA EUV will rely on computational lithography to provide accurate modeling of aberrations, compact 3D mask modeling, and expand inverse lithography to full-chip processing. Cadence's John Park argues for using a systematic and automated system for co-design and co-analysis of multi-die packages to reduce the margin for human e... » read more

Optimizing EDA Cloud Hardware And Workloads
By Aharon Etengoff - 04 Mar, 2024 - Comments: 0

Optimizing EDA hardware for the cloud can shorten the time required for large and complex simulations, but not all workloads will benefit equally, and much more can be done to improve those that can. Tens of thousands of GPUs and specialized accelerators, all working in parallel, add significant and elastic compute horsepower for complex designs. That allows design teams to explore various a... » read more

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