Verification And Test Of Safety And Security


Functional verification can cost as much as design, but new capabilities are piling onto an already stressed verification methodology, leaving solutions fragmented and incomplete. In a perfect world, a semiconductor device would be verified to operate according to its complete specification, and continue to operate correctly over the course of its useful life. The reality, however, is this i... » read more

The True Cost Of Software Changes


Safety and security are considered to be important in a growing number of markets and applications. Guidelines are put in place for the processes used to develop either the hardware or the software, but what they seem to ignore is that neither exists in a vacuum. They form a system when put together. Back when I was developing tools for hardware-software co-verification, there were fairly co... » read more

A Buyers Guide To An NPU


Choosing the right AI inference NPU (Neural Processing Unit) is a critical decision for a chip architect. There’s a lot at stake because as the AI landscape constantly changes, the choices will impact overall product cost, performance, and long-term viability. There are myriad options regarding system architecture and IP suppliers, and this can be daunting for even the most seasoned semicondu... » read more

Reducing Noise Issues In Microcontroller Systems: Part 1


In my ideal digital world, of which I often dream, signal voltage margins are always positive, signal timing margins are always positive, power supply voltages are always within the operating voltage range, and our environment is completely benign. Unfortunately, none of us live in this ideal world, no matter how much I would like to. The real world is dirty and noisy, and the power distribu... » read more

Overcoming Regression Debug Challenges With Machine Learning


Development of a modern semiconductor requires running many electronic design automation (EDA) tools many times over the course of the project. Every stage, from architectural exploration and design to final implementation and manufacturing preparation, has multiple methodology loops that must be repeated again and again. Even in such a complex development flow, functional simulation stands ... » read more

Better Choreography Required For Complex Chips


The rapidly growing number of features and options in chip design are forcing engineering teams to ratchet up their planning around who does what, when it gets done, and how various components will interact. In effect, more elements in the design flow need to be choreographed much more precisely. Some steps have to shift further left, while others need to be considered earlier in the plannin... » read more

Revolutionizing Product Development And User Experience: The Transformative Power Of Generative AI


Generative AI has become a prominent and versatile solution across various domains, including chip and system development. Its progress and impact have outpaced many other technological advancements, significantly benefiting numerous areas. In the semiconductor industry, EDA tools with generative AI have already established their position by offering unparalleled optimization capabilities. Thes... » read more

Developing A Customized RISC-V Core For MEMS Sensors


We recently described how Codasip Labs is working with the NimbleAI project to push the boundaries of neuromorphic vision. Let’s talk about another cool project. This project is focused on another sense, hearing. We will use our unique Codasip Studio design toolset to develop a customized RISC-V core for MEMS (micro-electro-mechanical system) sensors. Again, technology is inspired by bio... » read more

What’s The Buzz At The Battery Show?


Hwee Yng Yeo catches up with Christian Loew, Keysight’s solution manager for battery pack and module test, to find out what was abuzz on the floor of The Battery Show in Stuttgart recently. Hwee Yng: Christian, could you tell us what was the main buzz at The Battery Show this year? Christian: There were two topics topping the buzz list at the show – on the R&D side, new sodium i... » read more

Shift Left With Calibre To Optimize IC Design Flow Productivity, Design Quality, And Time To Market


Every IC designer strives to create a “clean,” or error-free, cell, block, chiplet, SoC, or 3DIC assembly before passing their work downstream for full sign-off verification. However, waiting until sign-off verification to find out how well you did is probably the least efficient approach to achieving production-ready layouts, impacting engineer productivity, project schedules, and hardware... » read more

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